Task-SwitchingProgram ModelConceptual Program-ModelTask IsolationMulti-taskingContext-SwitchingHow to cause a task-switch‘ljmp’ and ‘lcall’The two TSS formatsThe 80286 TSS formatThe 80386 TSS formatWhich to use: ‘ljmp’ or ‘lcall’?No Task Reentrancy!Task-NestingThe NT-bit in FLAGSTask-switch SemanticsTask-Gate Descriptor‘Threads’ versus ‘Tasks’A task with multiple threadsDemo program: ‘twotasks.s’A thread could use an LDTLDT descriptorsIn-class Exercise #1More enhancements?In-class Exercise #2Task-SwitchingHow the x86 processor assists with context-switching among multiple program-threadsProgram Model•Programs consist of data and instructions•Data consists of constants and variables, which may be ‘persistent’ or ‘transient’•Instructions may be ‘private’ or ‘shared’•These observations lead to a conceptual model for the management of programs, and to special processor capabilities that assist in supporting that conceptual modelConceptual Program-ModelTEXTDATABSSSTACKheapruntime library Private Instructions (persistent) Initialized Data (persistent) Uninitialized Data (persistent)Private Data (transient)Shared Instructions and Data (persistent)created at compile timecreated duringruntimeTask Isolation•The CPU is designed to assist the system software in isolating the private portions of one program from those of another while they both are residing in physical memory, while allowing them also to share certain instructions and data in a controlled way•This ‘sharing’ includes access to the CPU, whereby the tasks take turns at executingMulti-taskingTEXTDATABSSheapSTACKTEXTDATABSSheapSTACKshared runtime libraryuser-space (ring3)supervisor-space (ring0)TSS 1 TSS 2Task #1Task #2GDTIDTIDTRGDTRCSDSSSSPIPTRContext-Switching•The CPU can perform a ‘context-switch’ to save the current values of all its registers (in the memory-area referenced by the TR register), and to load new values into all its registers (from the memory-area specified by a new Task-State Segment selector)•There are four ways to trigger this ‘task-switch’ operation on x86 processorsHow to cause a task-switch•Use an ‘ljmp’ instruction (long jump):ljmp $task_selector, $0•Use an ‘lcall’ instruction (long call):lcall $task_selector, $0•Use an ‘int-n’ instruction (with a task-gate):int $0x80•Use an ‘iret’ instruction (with NT=1):iret‘ljmp’ and ‘lcall’•These instructions are similar – they both make use of a ‘selector’ for a Task-State Segment descriptorBase[ 15..0 ] Limit[ 15..0 ]Base[31..24]DPLBase[23..16]type0PTSS Descriptor-Formattype: 16bitTSS( 0x1=available or 0x3=busy) or 32bitTSS( 0x9=available or 0xB=busy)0 0 0Limit[19..16]AVLThe two TSS formats•Intel introduced the Task-State Segment in the 80286 processor (used in IBM-PC/AT)•The 80286 CPU had a 16-bit architecture•Later Intel introduced its 80386 processor which had a 32-bit architecture requiring a larger and more elaborate format for its Task-State Segment data-structure•The 286 TSS is now considered ‘obsolete’The 80286 TSS formatlinksp0ss0sp1ss1sp2ss2IPFLAGSAXCXDXBXSPBPSIDIESCSSSDSLDTR22 words16-bits= field is ‘static’= field is ‘volatile’024681012141618202224262830323436384042The 80386 TSS formatlinkesp0ss0esp1ss1esp2ss2PTDBEIPss0 ss0ss0 ss0ss0 ss0ss0 ss0ss0 ss0ss0 ss0ss0 ss0ss0 ss0ss0 ss0ESCSSSDSFSGSLDTRIOMAP TRAPEFLAGSEAXECXEDXEBXESPEBPESIEDII/O permission bitmap= field is ‘static’= field is ‘volatile’= field is ‘reserved’0481216202428323640444852566064687276808488929610026 longwords32-bitsWhich to use: ‘ljmp’ or ‘lcall’?•Use ‘ljmp’ to switch to a different task in case you have no intention of returning•Use ‘lcall’ to switch to a different task in case you want to ‘return’ to this task later•The CPU treats ‘ljmp’ and ‘lcall’ differently in regard to the TSS, GDT and EFLAGSNo Task Reentrancy!•Since each task has just one ‘save area’ (in its TSS), it must not not be permitted for a task to be recursively reentered! •The CPU enforces this prohibition using a ‘busy’ bit within each task’s TSS descriptor•Whenever the TR register is loaded with a new selector-value, the CPU checks to be sure the task isn’t already ‘busy’; if it’s not, the task is entered, but gets marked ‘busy’Task-Nesting•But it’s OK for one task to be nested within another, and another, and another…TSS#4TRLINKcurrent TSSTSS#3LINKTSS#2LINKTSS#1LINKlcalllcalllcall initial TSSThe NT-bit in FLAGS•When the CPU switches to a new task via an ‘lcall’ instruction, it sets NT=1 in FLAGS (and it leaves the old TSS marked ‘busy’)•The new task can then ‘return’ to the old task by executing an ‘iret’ instruction (the old task is still ‘busy’, so returning to it with an ‘lcall’ or an ‘ljmp’ wouldn’t be possible)Task-switch SemanticsField ljmp effect lcall effect iret effectnew busy-bit changes to 1changes to 1stays = 1old busy-bit is cleared stays = 1 is clearednew NT-flag Is cleared Is set to 1 no changeold NT-flag no change no change is clearednew LINK-field no change new value no changeold LINK-field no change no change no changeTask-Gate Descriptor•It is also possible to trigger a task-switch with a software or hardware interrupt, by using a Task-Gate Descriptor in the IDTTask-State Segment SelectorDPLPtype(=0x5)0Task-Gate Descriptor Format‘Threads’ versus ‘Tasks’•In some advanced applications, a task can consist of multiple execution-threads•Like tasks, threads take turns executing (and thus require ‘context-switching’)•CPU doesn’t distinguish between ‘threads’ and ‘tasks’ – context-switching semantics are the same for both•Difference lies in ‘sharing’ of data/codeA task with multiple threadsCODE 1 CODE 2DATA 1STACK 1 STACK 2heapTEXT (some shared, some private)DATA (some shared, some private)STACKS (each is thread-private)DATA 2user-space (ring3)supervisor-space (ring0)TSS 1 TSS 2Each thread has its own TSS-segmentDemo program: ‘twotasks.s’•We have constructed a simple demo that illustrates the CPU task-switching ability•It’s one program, but with two threads•Everything is in one physical segment, but the segment-descriptors create a number of different overlapping ‘logical’ segments•One task is the ‘supervisor’ thread: it ‘calls’ a ‘subordinate’ thread (to print a