Prelude to MultiprocessingCPUIDIntel x86 EFLAGS registerBut what if there’s no EFLAGS?Detecting 32-bit processorsDetecting EFLAGSTesting for ID-bit ‘toggle’How does CPUID work?Version and FeaturesSome Feature Flags in EDXSome Feature Flags in ECXMultiprocessor SpecificationMP Floating Pointer StructureAn example recordOur ‘mpinfo.cpp’ utilityA processor’s Local-APICLocal-APIC’s register-spaceAnalogies with the PICNew way to do ‘EOI’Each CPU has its own timer!Timer’s Local Vector TableTimer’s ‘Divide-Configuration’Initial and Current CountsUsing the timer’s interruptsIn-class exercise #1In-class exercise #2Prelude to MultiprocessingDetecting cpu and system-board capabilities with CPUID and the MP Configuration TableCPUID•Recent Intel processors provide a ‘cpuid’ instruction (opcode 0x0F, 0xA2) to assist software in detecting a CPU’s capabilities•If it’s implemented, this instruction can be executed in any of the processor modes, and at any of its four privilege levels•But this ‘cpuid’ instruction might not be implemented (e.g., 8086, 80286, 80386)Intel x86 EFLAGS register0 0 0 0 0 0 0 0 0 0IDVIPVIFACVMRF0NTIOPLOFDFIFTFSFZF0AF0PF1CF31 1615 021Software can ‘toggle’ the ID-bit (bit #21) in the 32-bit EFLAGS register if the processor is capable of executing the ‘cpuid’ instructionBut what if there’s no EFLAGS?•The early Intel processors (8086, 80286) did not implement any 32-bit registers •The FLAGS register was only 16-bits wide•So there was no ID-bit that software could try to ‘toggle’ (to see if ‘cpuid’ existed)•How can software be sure that the 32-bit EFLAGS register exists within the CPU?Detecting 32-bit processors•There’s a subtle difference in the way the logical shift/rotate instructions work when register CL contains the ‘shift-factor’•On the 32-bit processors (e.g., 80386+) the value in CL is truncated to 5-bits, but not so on the 16-bit CPUs (8086, 80286)•Software can exploit this distinction, in order to tell if EFLAGS is implementedDetecting EFLAGS# Here’s a test for the presence of EFLAGSmov $-1, %ax # a nonzero value mov $32, %cl # shift-factor of 32shl %cl, %ax # do logical shiftor %ax, %ax # test result in AXjnz is32bit # EFLAGS presentjmp is16bit # EFLAGS absentTesting for ID-bit ‘toggle’# Here’s a test for the presence of the CPUID instructionpushfl # copy EFLAGS contentspop %eax # to accumulator registermov %eax, %edx # save a duplicate imagebtc $21, %eax # toggle the ID-bit (bit 21)push %eax # copy revised contentspopfl # back into EFLAGSpushfl # copy EFLAGS contentspop %eax # back into accumulatorxor %edx, %eax # do XOR with prior valuebt $21, %eax # did ID-bit get toggled?jc y_cpuid # yes, can execute ‘cpuid’jmp n_cpuid # else ‘cpuid’ unimplementedHow does CPUID work?•Step 1: load value 0 into register EAX•Step 2: execute ‘cpuid’ instruction•Step 3: Verify ‘GenuineIntel’ character-string in registers (EBX,EDX,ECX)•Step 4: Find maximum CPUID input-value in the EAX register• load 1 into EAX and execute CPUID•Processor model and stepping information is returned in register EAXVersion and FeaturesExtendedFamily IDExtendedModel IDTypeFamilyIDModelSteppingID27 20 19 16 13 12 11 8 7 4 3 0Some Feature Flags in EDXHTTPGEAPICPSEDEVMEFPU9 328HTT = HyperThreading Technology (1 = yes, 0 = no)PGE = Page Global Entries (1=yes, 0=no) APIC = Advanced Programmable Interrupt Controller on-chip (1 = yes,0 = no)PSE = Page-Size Extensions (1 = yes, 0 = no)DE = Debugging Extensions (1=yes, 0=no)VME = Virtual-8086 Mode Enhancements (1 = yes, 0 = no)FPU = Floating-Point Unit on-chil (1=yes, 0=no)12 013Some Feature Flags in ECXVMX5VMX = Virtual Machine Extensions (1 = yes, 0 = no)Multiprocessor Specification•It’s an industry standard, allowing OS software to use multiple processors in a uniform way•OS software searches in three regions of the physical address-space below 1-megabyte for a “paragraph-aligned” data-structure of length 16-bytes called the MP Floating Pointer Structure: –Search in lowest KB of Extended Bios Data Area–Search in topmost KB of conventional 640K RAM–Search in the 128KB ROM-BIOS (0xE0000-0xFFFFF)MP Floating Pointer Structure•This structure may contain an ID-number for one a small number of standard SMP system architectures, or may contain the memory address for a more extensive MP Configuration Table having entries that specify a “customized” system architecture •The machines in our classroom employ the latter of these two optionsAn example record•The MP Configuration Table will contain a record for each logical processorCPU FlagsBP (bit 1), EN (bit 0)Local-APICversionLocal-APICIDEntry Type0CPU signature (stepping, model, family)Feature Flagsreserved (=0)reserved (=0)BP = Bootstrap Processor (1=yes, 0=no), EN = Enabled (1=yes, 0=no)Our ‘mpinfo.cpp’ utility•We created a Linux utility that will display the system-information contained in the MP Configuration Table (in hex format)•You can refer to the ‘MP Specification 1.4’ document (online) to interpret this display•This utility needs a device-driver ‘dram.c’ to be pre-installed (in order that it be able to directly access the system’s memory)A processor’s Local-APIC•The purpose of each processor’s APIC is to allow the CPUs in a multiprocessor system to send messages to one another and to manage the delivery of the interrupt-requests from the various peripheral devices to one (or more) of the CPUs in a dynamically programmable way•Each processor’s Local-APIC has a variety of registers, all ‘memory mapped’ to paragraph-aligned addresses within the 4KB page at physical-address 0xFEE00000Local-APIC’s register-spaceAPIC0xFEE00000 4GB physicaladdress-space0x00000000RAMAnalogies with the PIC•Among the registers in a Local-APIC are these (which had analogues in the older 8259 PIC’s design:–IRR: Interrupt Request Register (256-bits)–ISR: In-Service Register (256-bits)–TMR: Trigger-Mode Register (256-bits)•For each of these, its 256-bits are divided among eight 32-bit register addressesNew way to do ‘EOI’•Instead of using a special End-Of-Interrupt command-byte, the Local-APIC contains a dedicated ‘write-only’ register (named the EOI Register) which an Interrupt Handler writes to when it is ready to signal an EOI# issuing EOI to the