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USF CS 630 - Resolving interrupt conflicts

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Resolving interrupt conflictsIntel’s “reserved” interruptsExceptions in Protected-ModeHandling these conflictsLearning to program the 8259AThree internal registersPC System DesignHow to program the 8259AHow to access the IMRHow to read the master IRRSlide 11End-of-InterruptSome EOI examplesInitializing the master PICSlide 15Unused real-mode ID-rangeOther ideas in the demoThe Macro’s expansionHow ‘action’ worksThe stack statesThe on-screen status-lineIn-class exerciseICW1 and ICW2ICW3ICW4Resolving interrupt conflictsAn introduction to reprogramming of the 8259A Interrupt ControllersIntel’s “reserved” interrupts•Intel has reserved interrupt-numbers 0-31 for the processor’s various exceptions•But only interrupts 0-4 were used by 8086•Designers of the early IBM-PC ROM-BIOS disregarded the “Intel reserved” warning•So interrupts 5-31 got used by ROM-BIOS for its own various purposes•This created interrupt-conflicts for 80286+Exceptions in Protected-Mode•The interrupt-conflicts seldom arise while the processor is executing in Real-Mode•PC BIOS uses interrupts 8-15 for devices (such as timer, keyboard, printers, serial communication ports, and diskette drives)•CPU uses this range of interrupt-numbers for various processor exceptions (such as page-faults, stack-faults, protection-faults)Handling these conflicts•There are two ways we can ‘resolve’ these interrupt-conflicts when we write ‘handlers’ for device-interrupts in the overlap range–We can design each ISR to query the system in some way, to determine the ‘cause’ for the interrupt-condition (i.e., a device or the CPU) –We can ‘reprogram’ the Interrupt Controllers to use non-conflicting interrupt-numbers when the peripheral devices trigger an interruptLearning to program the 8259A•Either solution will require us to study how the system’s two Programmable Interrupt Controllers are programmed•Of the two potential solutions, it is evident that greater system efficiency will result if we avoid complicating our interrupt service routines with any “extra overhead” (i.e., of checking which event caused an interrupt)Three internal registersIRRIMRISR8259AIRR = Interrupt Request RegisterIMR = Interrupt Mask RegisterISR = In-Service Registeroutput-signal input-signalsPC System Design8259APIC(slave)8259APIC(master)CPUINTR Programming is viaI/O-ports 0xA0-0xA1 Programming is viaI/O-ports 0x20-0x21How to program the 8259A•The 8259A has two modes:–Initialization Mode–Operational Mode•Operational Mode Programming:–Write a (9-bit) command to the PIC–Maybe read a return-byte from the PIC•Initialization Mode Programming:–Write a complete initialization sequenceHow to access the IMR•If in operational mode, the Interrupt Mask Register (IMR) can be read or written at any time (by doing in/out with A0-line=1)–Read the master IMR: in al, #0x21–Write the master IMR: out #0x21, al–Read the slave IMR: in al, #0xA1–Write the slave IMR: out #0xA1, alHow to read the master IRR•Issue the “read register” command-byte, with RR=1 and RIS=0; read return-byte:mov al, #0x0Bout #0x20, alin al, #0x20How to read the master ISR•Issue the “read register” command-byte, with RR=1 and RIS=1; read return-byte:mov al, #0x0Aout #0x20, alin al, #0x20End-of-Interrupt•In operational mode (unless AEOI was programmed), the interrupt service routine must issue an EOI-command to the PIC•This ‘clears’ an appropriate bit in the ISR and allows other unmasked interrupts of equal or lower priority to be issued•The non-specific EOI-command clears the In-Service Register’s highest-priority bitSome EOI examples•Send non-specific EOI to the master PIC:mov al, #0x20out #0x20, al•Send non-specific EOI to both the PICs:mov al, #0x20out #0xA0, alout #0x20, alInitializing the master PIC•Write a sequence of four command-bytes•(Each command is comprised of 9-bits)00 0 0 1 0 0 0 1110 0 0 0 0 1 0 010 0 0 0 0 0 0 1A0 D7 D6 D5 D4 D3 D2 D1 D0ICW1=0x11ICW2=baseIDICW3=0x04ICW4=0x01Initializing the slave PIC•Write a sequence of four command-bytes•(Each command is comprised of 9-bits)00 0 0 1 0 0 0 1110 0 0 0 0 0 1 010 0 0 0 0 0 0 1A0 D7 D6 D5 D4 D3 D2 D1 D0ICW1=0x11ICW2=baseIDICW3=0x02ICW4=0x01Unused real-mode ID-range•We can use our ‘showivt.cpp’ demo to see the “unused” real-mode interrupt-vectors•One range of sixteen consecutive unused interrupt-vectors is 0x90-0x9F•We created a demo-program (‘reporter.s’) to ‘reprogram’ the 8259s to use this range•This could be done in protected-mode, too•It would resolve the interrupt-conflict issueOther ideas in the demo•It uses an assembly language ‘macro’ to create sixteen different ISR entry-points:MACRO isrpushfpush #?1call actionMEND •All the instances of the macro call to a common interrupt-handling procedure (named ‘action’)The Macro’s expansion•If the macro-definition is invoked, with an argument equal to, say, 8, like this:isr(8)then the ‘as86’ assembler will ‘expand’ the macro-invocation, replacing it with:pushfpush #8call action•Upon entering the ‘action’ procedure, the system stack has six words:•The two “topmost” words (at bottom of picture) will get replaced by the interrupt-vector corresponding to ‘int-ID’How ‘action’ worksFLAGSCSIPFLAGSInterrupt-IDreturn-from-actionSS:SPThe stack statesFLAGS FLAGS FLAGS FLAGSCSIPCS CS CSIP IP IPFLAGSInt-IDaction-returnFLAGSvector-HIvector-LOStage 1Stage 2 Stage 3Stage 4Upon entering ‘isr’ Upon entering ‘action’ Before exiting ‘action’ After exiting ‘action’(and entering ROM-BIOS interrupt- handler)The on-screen status-line•We call ROM-BIOS services to setup the video display-mode for 28-rows of text•We use lines 0 through 24 for the standard 80-column by 25-rows of text output•Line 25 is kept blank (as visual separator)•Lines 26 and 27 are used to show sixteen labeled interrupt-counters (IRQ0-IRQ15)•Any device-interrupt increments a counterIn-class exercise•The main new idea was reprogramming of the two 8259A Interrupt Controller, in order to avoid “overloading” of the Intel reserved interrupt-numbers (0x00-0x1F)•Modify our ‘tickdemo.s’ program so that a timer-tick interrupt in protected-mode will get routed through Interrupt Gate 0x20 (instead of through “reserved” Gate 0x08)ICW1 and ICW20A7 A6 A51LTIM ADI SNGL


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