IA32 Paging SchemeWhat is ‘paging’?What’s ‘paging’ good for?Why use ‘Paging’?How to enable pagingSeveral ‘paging’ schemesTerminologyControl Register CR3Two-Level Translation SchemePage-DirectoryAddress-translationIdentity-mappingAdditional mappingsDemo programDemo’s page-mappingVirtual-to-PhysicalThe demo’s table-entriesThe segment descriptorsPage-Level ‘protection’Format of a Page-Table entryFormat of a Page-Directory entryViolationsThe Error-Code formatControl Register CR2Slide 25Extensions to ‘paging’ schemeControl Register CR4What about efficiency?The ‘TLB’ solution4-way set-associativeIA32 Paging SchemeIntroduction to the Intel x86’s support for “virtual” memoryWhat is ‘paging’?•It’s a scheme for dynamically remapping addresses for fixed-size memory-blocks Virtual address-spacePhysical address-spaceWhat’s ‘paging’ good for?•For efficient ‘time-sharing’ among multiple tasks, an operating system needs to have several programs residing in main memory at the same time •To accomplish this using actual physical memory-addressing would require doing address-relocation calculations each time a program was loaded (to avoid conflicting with any addresses already being used)Why use ‘Paging’? •Use of ‘paging’ allows ‘relocations’ to be done just once (by the linker), and every program can ‘reuse’ the same addresses Task #1Task #2Task #3 physical memoryHow to enable pagingPGCDNWAMWPNEETTSEMMPPEControl Register CR0‘Protected-Mode’ must be enabled (PE=1)Then ‘Paging’ can be enabled (set PG=1)# Here is how you can enable paging (if CPU is in protected-mode)mov %cr0, %eax # get current machine status bts $31, %eax # turn on the PE-bit’s imagemov %eax, %cr0 # put modified status in CR0jmp . + 2 # now flush the prefetch queue# but you had better prepare the ‘mapping’ beforehand! 31 0Several ‘paging’ schemes•Intel’s design for ‘paging’ has continued to evolve since its introduction in 80386 CPU•Our Core-2 Quad CPUs support the initial ‘paging’ design (plus several extensions)•Here we shall describe the initial design (it’s simplest and it remains the ‘default’) •It is based on subdividing the entire 4GB physical address-space into 4-KB blocksTerminology•The 4KB memory-blocks are called ‘page frames’ -- and they are non-overlapping•Therefore each page-frame begins at a memory-address which is a multiple of 4K•Remember: 4K = 4 x 1024 = 4096 = 212•So the address of any page-frame will have its lowest 12-bits equal to zeros•Example: page six begins at 0x00006000Control Register CR3•Register CR3 is used by the CPU to find the paging-tables in memory which define its ‘virtual-to-physical’ address-translation•Specifically, CR3 points to a page-frame, called the Page Directory, which contains addresses of frames called Page Tables •An address in CR3 must be ‘page aligned’Physical Address of the Page-Directory31 0CR3 =Two-Level Translation Scheme PAGEDIRECTORYCR3 PAGETABLES PAGEFRAMESPage-Directory•The Page-Directory occupies one frame, so it has room for 1024 4-byte entries•Each page-directory entry can contain a pointer to a further data-structure, called a Page-Table (also page-aligned 4KB size)•Each Page-Table occupies one frame and has enough room for 1024 4-byte entries•Page-Table entries can contain pointersAddress-translation•The CPU examines any virtual address it encounters, subdividing it into three fields offset into page-frame index intopage-directory index into page-table31 22 21 12 11 0 10-bits 10-bits 12-bits This field selects one of the 1024 array-entries inthe Page-Directory This field selects one of the 1024 array-entries in that Page-Table This field provides the offset to one of the 4096 bytes in that Page-FrameIdentity-mapping•When the CPU first turns on the ‘paging’ capability, it must be executing code from an ‘identity-mapped’ page (or it crashes!)codecode physical memory ‘virtual’ memory identity-mappingAdditional mappings•Besides having at least one page that is ‘identity-mapped’ (for turning ‘paging’ on), there can be multiple other mappings codecode physical memory ‘virtual’ memory identity-mappingdatadatadatadataDemo program•We wrote a very simple demo-program showing how to create a Page-Directory and a Page-Table for an identity-mapping of the page-frame that contains program-code, plus a non-identity mapping for the initial page of the video display memory•This demo is named ‘vrampage.s’ (you can find it on our CS 630 course website)Demo’s page-mapping program arena video memory unused unused unusedCR3 page-directory one page-table Our ‘vrampage.s’ demo-program uses only four page-frames of physical memory (16K) 1) the program’s arena (at 0x00010000) 2) the page-directory (at 0x00011000) 3) only one page-table (at 0x00012000) 4) one page of vram (at 0x000B8000)Virtual-to-Physical physical address-space ‘virtual’ address-spacecode and data video memory page-table video memory code and data0x00010000 0x000100000x000B80000x00000000 page-directoryThe demo’s table-entries•Our page-directory uses only one entry:•And our page-table uses only two entries:0x00011 003 pgdir[0x000]:0x000B8 003 pgtbl[0x000]:0x00010 003 pgtbl[0x010]: identity-mappingThe segment descriptors•Our demo’s GDT uses three descriptors:0x0000009A010000FFFF ‘executable’ segment at virtual-address 0x000100000x00000092010000FFFF ‘writable’ segment at virtual-address 0x000100000x00000092000000FFFF ‘writable’ segment at virtual-address 0x00000000Page-Level ‘protection’•Each entry in a Page-Table can assign a collection of ‘attributes’ to the Page-Frame it points to; for example:–The P-bit (page is ‘present’) can be used by an operating system to implement “demand paging” and “memory-mapping” of disk-files–The W/R-bit can be used to mark a page as either ‘Writable’ (=1) or as ‘Read-Only’ (=0) –The U/S-bit can be used to mark a page as ‘User-accessible’ or as ‘Supervisor-only’Format of a Page-Table entryPAGE-FRAME BASE ADDRESS PWUPWTPCDAD0031 12 11 10 9 8 7 6 5 4 3 2 1 0AVAILLEGEND P = Present (1=yes, 0=no) W = Writable (1 = yes, 0 = no) U = User (1 = yes, 0 = no) A = Accessed (1 = yes, 0 = no) D = Dirty (1