1244 Lecture Notes 11-11RTL and BehavioralSynthesisSrinivas DevadasMITKurt KeutzerRichard NewtonUC Berkeley2RTL Synthesis FlowRTLSynthesisHDLnetlistlogicoptimizationnetlistLibraryphysicaldesignlayoutabsq01dclkabsq01dclk2244 Lecture Notes 11-13An RTL description is always implicitly structural -• the registers and their interconnectivity are defined• Thus the clock-to-clock behavior is defined• Only the control logic for the transfers is synthesized. This approach can be enhanced:• Register inferencing• Automating resource allocation++1*RTL impliesbcade2RTL levela = b + c;d = a + 1;e = d * 2;Behavioral impliese = 2 * (b + c + 1)4Behavioral Synthesis FlowRTLSynthesisHDLnetlistlogicoptimizationnetlistLibraryphysicaldesignlayoutabsq01dclkabsq01dclkHDLBehavioralSynthesis3244 Lecture Notes 11-15A behavioral description is always functional• Temporal relationships are only expressed as precedences• An entire micro-architecture is synthesized from the behavioral descriptionThe two key elements of behavioral transformation:• Automating resource allocation (could be RTL also)• Scheduling ++1*RTL impliesbcade2Behavioral levela = b + c;d = a + 1;e = d * 2;Behavioral impliese = 2 * (b + c + 1)6Two Steps:1. Translation from RTL description into gates2. Optimization of logicIdeally, all of the intelligence should be in the optimization stepUnfortunately, starting point for optimization affects results⇒ Need to write a “good” RTL descriptionRTL Synthesis4244 Lecture Notes 11-17entity VHDL isport C (A, B, C : in BIT ;Z : out BIT ;     ) ;end VHDL;architecture VHDL_1 of VHDL isbegin   Z(A and B) or C ; }end VHDL_1 ;entity and port declarationsdefine interfacedefinesimplementationlogic expressionABCVHDL Z8process beginwait until CLOCK’event and CLOCK = ‘1’ ;if (ENABLE = ‘1’) thenTOGGLE = not TOGGLE;end if;end process;wait infers a flip-flop>TOGGLEENABLECLOCKWait Statements5244 Lecture Notes 11-19Current scenario: Designer iterates over RTL descriptions using simulation and synthesis tools to verify and evaluate designPROBLEM: Equivalent RTL descriptions may result in dramatically different logic circuits in terms of area/performance EVEN AFTER OPTIMIZATION.Writing RTL Descriptions10push multiplexors to inputs_+abSUBresult10resultab-bSUBEquivalent RTL Descriptionsif (SUB)result = a - b;elseresult = a + b;if (SUB)b = -b;result = a + b;+106244 Lecture Notes 11-1111. Increase power of optimization.2. Define “good” input and restrict oneselfto writing “good” input descriptions.3. Manipulate input descriptions to make them “good”.Rules for writing descriptions based onknowledge that a library of descriptions are good starting points for synthesis.Practical Solution12Behavioral Synthesis FeaturesScheduling of operations– Operation Chaining and Multi-cycling– Different Scheduling Modes, and constraintsMemory Inferencing– Array’s can be mapped directly to RAM– Automatic control/data/address generation– RAM tradeoffs (1 port vs. 2 port) are easyAllocation of resources– Building your own design componentsUsing Pipelined Components– Multipliers, Adders, RAMs, othersPipelining Loop with various Throughput & LatencyAutomatic generation of FSM Controller and integration of Datapath7244 Lecture Notes 11-113Level of Acceptance of SynthesisTechniquesSource: A. DeGeusSpeed of De s ig ne rExpe rt des ig ne rBe havio ral S ynthe s isAc c e ptanc e curveQuality o f De s ig nSe que ntial S ynthes isCo mbinatio nal Synthe s is14Tradeoff Example - Echo Canceler8244 Lecture Notes 11-115Echo Canceler - TapTotal:6 Taps16Tap - Complex Multiplication16x2->18multiplication17x17->17addition17x17->17subtractionTotal: 6 complex multiplications9244 Lecture Notes 11-117Echo Canceler ComplexityClock cycle : 30nsComplexity : around 10K to 20K gatesModules : 16x2 multiplier : 22ns 713 gates17x17 add/sub : 20ns 193 gatesSource : ~2000 VHDL excl. commentsoperations handled by BC operations handled by DCaddition : 30 constant : 11subtraction : 20 logic oper. : 66multiplication : 24 word expand : 100compare oper. : 2 truncation : 124data select : 29 shift oper. : 62delay elements : 24Total : 49218Echo Canceler Source Codeuse work.COSSAP_PACKAGE_SYNOPSYS.all ;. . . . . . . . . port ( IN_R : in STD_LOGIC_VECTOR((WORDLENGTHIN-1) downto 0) ;. . . . . . . . . . . . . . architecture behavior of ec is. . . . . . . . . . . .ot := (in2 and mask) or (in1 and not mask) ;delay_line_M_6_7_7 := (others => STD_LOGIC_VECTOR(conv_signed(0,16)));delay_line_M_6_7_8 := (others => (others => ’0’));delay_line_M_6_7_5 := (others => (others => ’0’));delay_line_M_6_7_12 := (others => STD_LOGIC_VECTOR(conv_signed(0,16)));delay_line_M_6_6_7 := (others => STD_LOGIC_VECTOR(conv_signed(0,16)));delay_line_M_6_6_8 := (others => (others => ’0’));delay_line_M_6_6_5 := (others => (others => ’0’));delay_line_M_6_11_12 := (others => STD_LOGIC_VECTOR(conv_signed(0,16)));delay_line_M_6_14_7 := (others => STD_LOGIC_VECTOR(conv_signed(0,16)));delay_line_M_6_14_8 := (others => (others => ’0’));delay_line_M_6_14_5 := (others => (others => ’0’));delay_line_M_6_14_12 := (others => STD_LOGIC_VECTOR(conv_signed(0,16)));wait until CLOCK’event and CLOCK=’1’;M_6_7_11_11_SIG_0010 := SIGNED(M_6_7_11_11_SIG_0008) + SIGNED(M_6_7_11_11_SIG_0009);M_6_7_11_12_SIG_0010 := SIGNED(M_6_7_11_12_SIG_0009) -SIGNED(M_6_7_11_12_SIG_0008);M_6_7_9_11_SIG_0010 := SIGNED(M_6_7_9_11_SIG_0008) + SIGNED(M_6_7_9_11_SIG_0009);M_6_7_9_12_SIG_0010 := SIGNED(M_6_7_9_12_SIG_0009) -SIGNED(M_6_7_9_12_SIG_0008);M_6_7_6_SIG_0006 := signed(M_6_7_6_SIG_0017) * signed(M_6_7_6_SIG_0024);M_6_7_6_SIG_0009 := signed(M_6_7_6_SIG_0022) * signed(M_6_7_6_SIG_0019);M_6_7_6_SIG_0016 := signed(M_6_7_6_SIG_0018_1) * signed(M_6_7_6_SIG_0020);M_6_7_6_SIG_0013 := signed(M_6_7_6_SIG_0021) * signed(M_6_7_6_SIG_0023);delay_line_M_6_6_5 := M_6_6_SIG_0034 & delay_line_M_6_6_5(1 to 1-1);delay_line_M_6_6_5(1) := M_6_6_SIG_0034; delay_line_M_6_6_8 := M_6_6_SIG_0025 & delay_line_M_6_6_8(1 to 1-1);delay_line_M_6_6_8(1) := M_6_6_SIG_0025; M_6_6_11_11_SIG_0010 := SIGNED(M_6_6_11_11_SIG_0008) + SIGNED(M_6_6_11_11_SIG_0009);M_6_6_11_12_SIG_0010 := SIGNED(M_6_6_11_12_SIG_0009) -SIGNED(M_6_6_11_12_SIG_0008);M_6_6_9_11_SIG_0010 := SIGNED(M_6_6_9_11_SIG_0008) + SIGNED(M_6_6_9_11_SIG_0009);M_6_6_9_12_SIG_0010 := SIGNED(M_6_6_9_12_SIG_0009) -SIGNED(M_6_6_9_12_SIG_0008);M_6_6_6_SIG_0006 :=