11Design VerificationMike ButtsSynopsysProf. Kurt KeutzerEECSUC BerkeleyKurt Keutzer 2Design ProcessDesign: specify and enter the design intentImplement:refine the design through all phasesVerify:verify the correctness of design and implementation2Kurt Keutzer 3Design VerificationRTLSynthesisHDLnetlistlogicoptimizationnetlistLibrary/modulegeneratorsphysicaldesignlayoutmanualdesignspecificationIs the designconsistentwith the originalspecification?Is what I think I wantwhat I really want?Kurt Keutzer 4Implementation VerificationRTLSynthesisHDLnetlistlogicoptimizationnetlistLibrary/modulegeneratorsphysicaldesignlayoutmanualdesignIs the implementationconsistentwith the originaldesign intent?Is what I implementedwhat Iwanted?absq01dclkabsq01dclk3Kurt Keutzer 5Manufacture Verification (Test)RTLSynthesisHDLnetlistlogicoptimizationnetlistLibrary/modulegeneratorsphysicaldesignlayoutmanualdesignIs the manufacturedcircuitconsistentwith the implemented design?Did theybuildwhat Iwanted?absq01dclkabsq01dclkKurt Keutzer 6Design VerificationRTLSynthesisHDLnetlistlogicoptimizationnetlistLibrary/modulegeneratorsphysicaldesignlayoutmanualdesignspecificationIs the designconsistentwith the originalspecification?Is what I think I wantwhat I really want?4Kurt Keutzer 7Verification is an Industry-Wide IssueIntel: Processor project verification: “Billions of generated vectors”“Our VHDL regression tests take 27 days to run. ”Sun: Sparc project verification: Test suite ~1500 tests > 1 billion random simulation cycles“A server ranch ~1200 SPARC CPUs”Bull: Simulation including PwrPC 604“Our simulations run at between 1-20 CPS.” “We need 100-1000 cps.”Cyrix : An x86 related project“We need 50x Chronologic performance today.”“170 CPUs running simulations continuously”Kodak: “hundreds of 3-4 hour RTL functional simulations”Xerox: “Simulation runtime occupies ~3 weeks of a design cycle”Ross: 125 Million Vector Regression testsDesign Teams are Desperate for Faster SimulationDesign Teams are Desperate for Faster SimulationKurt Keutzer 8The Verification Crisis2002PhysicalPhysicalImplementationImplementationDesignDesignCreationCreationVerificationVerification1995VerificationVerificationPhysicalPhysicalImplementationImplementationDesignDesignCreationCreationVerification Consumes Hardware Design CycleVerification Consumes Hardware Design Cycle5Kurt Keutzer 9Productivity Gap1Logic Transistors per Chip(K)ProductivityTrans./Staff -Mo.101001,00010,000100,0001,000,00010,000,000101001,00010,000100,0001,000,00010,000,000100,000,000Logic Tr./ChipTr./S.M.58%/Yr. compoundComplexity growth rate21%/Yr. compoundProductivity growth rateSource: SEMATECH198119831985198719891991199319951997199920032001200520072009xxxxxxx2.5µ.10µ.35µProductivity GapKurt Keutzer 10Verification Gap1Logic Transistors per Chip(K)ProductivityTrans./Staff -Mo.101001,00010,000100,0001,000,00010,000,000101001,00010,000100,0001,000,00010,000,000100,000,000Logic Tr./ChipTr./S.M.58%/Yr. compoundComplexity growth rate21%/Yr. compoundProductivity growth rateSource: SEMATECH198119831985198719891991199319951997199920032001200520072009xxxxxxx2.5µ.10µ.35µVerification Gap6Kurt Keutzer 11logic_transistorschipXlines_in_designlogic_transistorsbugsline_of_designX=bugschipWhy the Gap?Kurt Keutzer 12logic_transistorschipXlines_of_designlogic_transistorsbugslines_of_designX10,000,000 trschipX110110,000X=100 bugschipFilling in Reasonable Numbers7Kurt Keutzer 13logic_transistorschipXlines_of_designlogic_transistorsbugslines_of_designX10,000,000 trschipX1100110,000X=10 bugschipthis year!!Raising the Level of AbstractionKurt Keutzer 14logic_transistorschipXlines_of_designlogic_transistorsbugslines_of_designX1,000,000,000 trschipX1100110,000X=1000 bugschipMoore’s Law Implies More Bugs5 years!!8Kurt Keutzer 15The Verification BottleneckVerification problem grows even faster due to thecombination of increased gate count and increased vector count1990199620021M100M10B100k 10M1M10,000x more VectorsRequired to Validate100 x 10,000 = 1 million times more Simulation Load100x Gate CountKurt Keutzer 161 million instructions, assume 2 million cyclesToday’s verification choices:50M cps: 40 msec Actual system HW5M cps: 400 msec Logic emulator1(QT Mercury)500K cps: 4 sec Cycle-based gate accelerator1(QT CoBALT)50K cps: 40 sec Hybrid emulator/simulator2(Axis)5K cps: 7 min Event-driven gate accelerator2(Ikos NSIM)500 cps: 1.1 hr50 cps: 11 hr CPU and logic in HDL simulator3(VCS)5 cps: 4.6 days1: assumes CPU chip 2: assumes RTL CPU 3: assumes HDL CPUTime to boot VxWorksM. Butts - Synopsys9Kurt Keutzer 17Aspects of Design VerificationInitial SpecificationValidationInitial SpecificationValidationHDL FunctionalVerification(interactive)HDL FunctionalVerification(interactive)HDL FunctionalVerification(regressions)HDL FunctionalVerification(regressions)Implentatation In-SystemVerificationImplentatation In-SystemVerificationKurt Keutzer 18Phases of Design VerificationTimeBugs FoundBasic Functionality TapeoutFinding tough bugs is ad hoc & brute force¾ takes 80% of time, effort, & resources¾ represents most of the risk¾ is an unbounded problem10Kurt Keutzer 19Software Simulation – Application of simulation stimulus to model of circuitHardware Accelerated Simulation– Use of special purpose hardware to accelerate simulation of circuitEmulation– Emulate actual circuit behavior - e.g. using FPGA’sRapid prototyping – Create a prototype of actual hardwareFormal verification– Model checking - verify properties relative to model– Theorem proving - prove theorems regarding properties of a modelTechnologies for Design VerificationKurt Keutzer 20Matching Problems and TechnologiesEvent Driven– Interactive Phase– High flexibility– Quick turnaround time– Good debug capabilitiesCycle-based simulation– Regression Phase– Highest performance– Highest capacityEmulation and Acceleration– In-System Verification– Highest performance – Highest Capacity– Real system environmentEmulation/Rapid ProtypingCycle-basesimulationSpecificationValidationSpecificationValidationFunctionalVerification(interactive)FunctionalVerification(interactive)ImplementationVerificationImplementationVerificationFunctionalVerification(regressions)FunctionalVerification(regressions)In-SystemVerificationIn-SystemVerificationEquivalence CheckingEvent-driven Simulation11Kurt Keutzer 21Axis (Emulator) ViewKurt Keutzer 22Software Simulation – Application of