Berkeley ELENG 244 - Delay Modeling and Static Timing Verification

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1Delay Modeling and Static Timing VerificationProf. Kurt KeutzerMichael OrshanskyEECSUniversity of CaliforniaBerkeley, CA2RTL Synthesis FlowRTLSynthesisHDLnetlistlogicoptimizationnetlistLibraryphysicaldesignlayoutabsq01dclkabsq01dclk3Design ProcessDesign : specify and enter the design intentImplement:refine the design through all phasesVerify:verify the correctness of design and implementation4Implementation VerificationRTLSynthesisHDLnetlistlogicoptimizationnetlistLibrary/modulegeneratorsphysicaldesignlayoutmanualdesignIs the implementationconsistentwith the originaldesign intent?Is what I implementedwhat Iwanted?absq01dclkabsq01dclk5Implementation verification for ASIC’sRTLSynthesisHDLnetlistlogicoptimizationnetlistLibrary/modulegeneratorsphysicaldesignlayoutmanualdesignApply gate-level simulation (‘‘the golden simulator’’) at each step to verify functionality:• 0-1 behavior on regression test setand timing:• maximum delay of circuit across critical pathsabsq01dclkabsq01dclkASICsignoff6Advantages of gate-level simulation● verifies timing and functionality simultaneously● approach well understood by designersDisadvantages of gate-level simulation● computationally intensive - only 1 - 10 clock cycles of 100K gate design per 1 CPU second● incomplete - results only as good as your vector set - easy to overlook incorrect timing/behaviorSimulationdriver(vectors)Simulationmonitor(yes/no)andspeedSoftware Simulationabsq01dclk7Alternative - Static Sign-offRTLSynthesisHDLnetlistlogicoptimizationnetlistLibrary/modulegeneratorsphysicaldesignlayoutmanualdesignabsq01dclkabsq01dclkASICsignoffUse static analysis techniques to verify: functionality:• formal equivalence-checking techniquesand timing:• use static timing analysis8Different Roles of Timing AnalysisTiming verification● Adherence to particular timing requirementsTiming-driven optimization becomes critical with tighter timing closure● Placement● Routing● Gate and wire area minimizationTiming optimization● Identify timing-critical regions● Drive optimization to meet timing specs9• determine fastest permissible clock speed (e.g. 100MHz)by determining delay (including set-up and hold time) of longest path from register to register (e.g. 10ns.)•largely eliminates need for gate-level simulation to verify the delay of the circuitPurpose of Static Timing VerificationclkCombinationallogicclkCombinationallogicclkCombinationallogic10Cycle Time - Critical Path DelayCycle time (T) cannot be smaller than longest path delay (Tmax)Longest (critical) path delay is a function of:Total gate, wire delays● logic levelsclockQ1Q2Tclock1 Tclock2critical path, ~5 logic levelsTclock1datacycle timemaxT T≤11Cycle Time - Setup TimeFor FFs to correctly latch data, it must be stable during:• Setup time (Tsetup) beforeclock arrivesclockQ1Q2Tclock1 Tclock2critical path, ~5 logic levelsTclock1datasetup timemax setupT T T+ ≤12Cycle Time - Clock-skewclockQ1Q2Tclock1 Tclock2Tclock1Tclock2Q2dataclock skewQ212If clock network has unbalanced delay – clock skewCycle time is also a function of clock skew (Tskew)max setup skewT T T T+ + ≤critical path, ~5 logic levels13Cycle Time - Clock to QCycle time is also a function of propagation delay of FF (Tclk-to-Q)Tclk-to-Q: time from arrival of clock signal till change at FF output)clockQ1Q2Tclock1 Tclock2Tclock1Tclock2Q2clock-to-QdataQ2max setup skew clk to QT T T T T− −+ + + ≤critical path, ~5 logic levels14Min Path Delay - Hold TimeFor FFs to correctly latch data, data must be stable during:• Hold time (Thold) after clock arrivesDetermined by delay of shortest path in circuit (Tmin) and clock skew (Tskew)clockQ1Q2Tclock1 Tclock2short path, ~3 logic levelsTclock1datahold timemin hold skewT T T≥ +15One more timeset-up time – D stablebefore clockcycle timeExample of a single phase clockhold time –D stable after clockWhen signalmay change16Elements of Timing VerificationTo verify circuit timing need● Accurate delay calculation● Timing analysis engineDelay calculation● Delay numbers for gates and wiresTiming analysis engine● Circuit path analysis● Clocks17Delay Modeling and Delay ComputationSingle path delay computationDDTo simulate complex circuits, need accurate models of● Gate delay● Interconnect delaytG1tG2tW1tG3Time100%50%Path delay = sum of 50% propagation delaystG1tG2VddtW1tG318Gate Delay Modeling RequirementsFast delay evaluation ● To enable full chip simulation● Analytical models and look-up tablesConservative delay models● STA determines longest path delay under all possible conditionsTo enable fast tractable computation, have to give up on many modeling details● Input pattern dependencies● Complex dynamic behavior is captured through tables19Gate Timing Characterization“Extract” exact transistor characteristics from layout● Transistor width, length, junction area and perimeter● Local wire length and inter-wire distanceCompute all transistor and wire capacitancesCLDABFCL20Cell Timing CharacterizationDelay tables generated using a detailed transistor-level circuit simulator SPICE (differential-equations solver)For a number of different input slews and load capacitances simulate the circuit of the cell● Propagation time (50% Vdd at input to 50% at output)● Output slew (10% Vdd at output to 90% Vdd at output)TimetslewtpdVdd21Non-linear effects reflected in tablesInputSlewInputSlewDelay at the gateOutputCapacitanceOutputCapacitanceOutputSlewIntrinsicDelayResulting waveformDG= f (CL, Sin) and Sout= f (CL, Sin)● Non-linearInterpolate between table entriesInterpolation error is usually below 10% of SPICE22Conservatism of Gate Delay ModelingTrue gate delay depends on input arrival time patterns● STA will assume that only 1 input is switching● Will use worst slope among several inputsTimeAB FtpdTimeAFtpdVddVddDABFCLDABFCL23Wire-Dominated ChipsWiring requirements grow dramaticallyNumber of interconnect layers (6-8)Interconnect effects● Large RC and RLC delays● Inter-wire couplingInterconnect becomes a dominant factor in limiting chip performanceTSMC Cupper Process24Wire Delay ModelingLumped RC model● Simple: R – total resistance, C – total capacitance● Pessimistic and inaccurate● Spurious oscillationsDistributed RC model● Required for longer interconnect lines● Exact solution requires solving “diffusion equation”● No closed-form solution - approximationsR1C1R2C2RNCNVinVoutRC25Wire Delay Modeling:


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