Implications of Deep SubmicronSimplex SolutionsProf. A. Richard NewtonUniversity of California at BerkeleyPage 1Copyright © 1997, A. Richard NewtonEE244 Fall 97 6.2.1EE244: Design Technology for Integrated Circuits and SystemsOutlineLecture 6.2◆ Regular Module Structures▲ CMOS Synthetic Libraries▲ Weinberger Arrays▲ Gate Matrix▲ Programmable Logic Array (PLA)▲ Storage Logic Array (SLA)▲ Programmable Path Logic (PPL)◆ Automating the Design of Regular StructuresEE244 Fall 97 6.2.2Single-Strip Static CMOS Layout◆ Optimized for combinational strips in static CMOSVDDGNDPolysiliconN-Well (pMOS)P-Well (nMOS)Implications of Deep SubmicronSimplex SolutionsProf. A. Richard NewtonUniversity of California at BerkeleyPage 2Copyright © 1997, A. Richard NewtonEE244 Fall 97 6.2.3Single-Strip Static CMOS◆ X+YZCMOS Standard-Cell LayoutEE244 Fall 97 6.2.4Single-Strip Static CMOS◆ Optimized layout with ideal path and drain-sourcemergingImplications of Deep SubmicronSimplex SolutionsProf. A. Richard NewtonUniversity of California at BerkeleyPage 3Copyright © 1997, A. Richard NewtonEE244 Fall 97 6.2.5Programmable Logic Array◆ Symbolic LayoutEE244 Fall 97 6.2.6Single-Strip Static CMOS◆ X+YZCMOS Standard-Cell LayoutImplications of Deep SubmicronSimplex SolutionsProf. A. Richard NewtonUniversity of California at BerkeleyPage 4Copyright © 1997, A. Richard NewtonEE244 Fall 97 6.2.7Single-Strip Static CMOS◆ Dual graphs for P and N sidesEE244 Fall 97 6.2.8Optimization of Static Strip Layout◆ Uehara & Van Cleemput, 1981▲ Every gate-drain & gate-source potential is represented bya vertex.▲ Drains or sources at the same potential (connected) arerepresented by the same vertex.▲ Every transistor is represented by an edge connecting thedrain and source verticies of that transistor.▲ “If two edges x and y in in the graph are adjacent, then it ispossible to place the corresponding transistors inphysically adjacent positions of the same row, and henceconnect them by a diffusion area. In order to minimize thenumber of separation areas, it is necessary to find a set ofpaths, of minimum size, which corresponds to chains oftransistors in the row.”Implications of Deep SubmicronSimplex SolutionsProf. A. Richard NewtonUniversity of California at BerkeleyPage 5Copyright © 1997, A. Richard NewtonEE244 Fall 97 6.2.9Euler Path◆ Is a path with no repeating edges that contains allthe edges of the graph◆ If such a path does not exist, the graph can bepartitioned into subgraphs with Euler paths.◆ Must find paths in the dual graphs with the samesequence of edgesEE244 Fall 97 6.2.10Uehara and VanCleemput (1981)◆ Enumerate all possible decompositions of thegraph and find the minimum number of paths thatcover the graph◆ Chain the gates by means of shared diffusion areasaccording to the order of the edges in each Eulerpath◆ If more than two Euler paths are needed to coverthe graph model, provide separation betweenchains.Implications of Deep SubmicronSimplex SolutionsProf. A. Richard NewtonUniversity of California at BerkeleyPage 6Copyright © 1997, A. Richard NewtonEE244 Fall 97 6.2.11Heuristic Algorithm◆ Relies on the fact that if the number of inputs to everyAND/OR element is odd, then the corresponding graph hasa single Euler path and there exists a graph such that thesequence of edges on the Euler path corresponds to theorder of the inputs on a planar representation of the logicdiagram◆ Convert every even number of parallel (series) edges intoan odd one by adding pseudo pins◆ Minimize the interlace of pseudo pins and real pins◆ Find the Euler path (input sequence) and lay out the circuit◆ Delete pseudo pins and replace with separation areasEE244 Fall 97 6.2.12Single-Strip Static CMOSN-side Euler path: [1,3,2,4,5]Dual Euler path: [2,3,1,4,5]Implications of Deep SubmicronSimplex SolutionsProf. A. Richard NewtonUniversity of California at BerkeleyPage 7Copyright © 1997, A. Richard NewtonEE244 Fall 97 6.2.13Gate Matrix Layout◆ nMOS & pMOS implemented separatelyEE244 Fall 97 6.2.14Gate Matrix LayoutExample CircuitGate Matrix LayoutImplications of Deep SubmicronSimplex SolutionsProf. A. Richard NewtonUniversity of California at BerkeleyPage 8Copyright © 1997, A. Richard NewtonEE244 Fall 97 6.2.15Gate Matrix Layout◆ Abstract representation, the connection graph andthe interval