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11Manufacture Testing Manufacture Testing of of Digital CircuitsDigital CircuitsProf. K-T ChengUC Santa BarbaraProf. Srinivas DevadasMITProfs. Kurt Keutzer & Sanjit SeshiaMukul PrasadUniversity of CaliforniaBerkeley, CA2Design ProcessDesign: specify and enter the design intentImplement:refine the design through all phasesVerify:verify the correctness of design and implementation23Design VerificationRTLSynthesisHDLnetlistlogicoptimizationnetlistLibrary/modulegeneratorsphysicaldesignlayoutmanualdesignspecificationIs the designconsistentwith the originalspecification?Is what I think I wantwhat I really want?4Implementation VerificationRTLSynthesisHDLnetlistlogicoptimizationnetlistLibrary/modulegeneratorsphysicaldesignlayoutmanualdesignIs the implementationconsistentwith the originaldesign intent?Is what I implementedwhat Iwanted?absq01dclkabsq01dclk35Manufacture Verification (Test)RTLSynthesisHDLnetlistlogicoptimizationnetlistLibrary/modulegeneratorsphysicaldesignlayoutmanualdesignIs the manufacturedcircuitconsistentwith the implemented design?Did theybuildwhat Iwanted?absq01dclkabsq01dclk6TestingApply a sequence of inputs to a circuitObserve the output response and compare the response with a precomputed or “expected”responseAny discrepancy is said to constitute an error, the cause of which is a physical defectFAB?absq01dclk47Defects and Fault modelsManufacturing defects can manifest in a variety of ways:[See Ch. 5 of book]– Bridging– Contaminants– Shorts– Opens– Transistors stuck-openThese need to be reduced to models:– Single stuck-at-1, stuck-at-0– Multiple stuck-at-1, stuck-at-0– Delay fault models:• Gate• Path• x {hazard-free, hazard-free robust}Presently:– single-stuck-at fault model ubiquitous– some use of delay fault modeling9Defect Model: Stuck-At FaultsAny input or internal wire in circuit can be stuck-at-1 or stuck-at-0Single stuck-at-fault model: In the faulty circuit, a single line/wire is S-a-0 or S-a-1Multiple stuck-at fault model: In the faulty circuit any subset of wires are S-a-0/S-a-1 (in any combination)abf1f2ABCD510Reduce to Combinational Logic ProblemScan Flip-flopsCombinationalLogicadd additional state to flip-flops(15 - 20% area overhead)inputsoutputsScan-chainScan-chain11Outline of Topics• Basics & Terminology• PODEM technique• Boolean Satisfiability-based technique612Test GenerationChoose a fault model, e.g., single stuck-at fault modelGiven a combinational circuit which realizes the function f(x1, x2, . . . xn), a logical fault alters it to fαααα(x1, x2, . . . xn)Inputs detecting ααααare f ⊕⊕⊕⊕ fαααα( = 1 )Interested in one vectorA = (a1, a2, . . ., an) ∈∈∈∈ f ⊕⊕⊕⊕ fαααα13Single Stuck-At FaultsA fault is assumed to occur only on a single line.x1x2x3abGZ = x1x2+ x2x3a s-a-1 Z = x1 + x2x3G s-a-1 Z = x2x3x1x2x3abGThis model is used because it has been found to bestatistically correlated with defect-free circuits714Activation and Path SensitizationIn order for an input vector X to detect a fault h s-a-j, j = 0,1 the input X must cause the signal h in the normal (fault-free) circuit to take the value j.The condition is necessary but not sufficient. Error signal must be propagated to output.hfxs-a-1x2x3x1x4To detect h s-a-1,need x2+ x3= 0, i.e., x2x315The faulty signal must be propagated along some path from its origin to an outputG3Fault Activationh0/10/10/101How to activate the fault?G1G5fG4G2xx2x3x1x4816The faulty signal must be propagated along some path from its origin to an outputG3Fault Activationh0/10/10/101h s-a-1, for h to be 0, need x2= x3= 0 ( x2x3 )G1G5fG4G2xx2x3x1x417The error signal must be propagated along some path from its origin to an outputHow to propagate the fault?G3Fault Propagationh0/1h s-a-1, for h to be 0, need x2= x3= 0 ( x2x3 )G1G5fG4G2xx2x3x1x4918The error signal must be propagated along some path from its origin to an outputOnly one path G3, G5In order to propagate an error through AND gate G3, other input x1= 1. To propagate through G5, need G4= 0, x1+ x4G3Fault Propagationh0/10/10/101h s-a-1, for h to be 0, need x2= x3= 0 ( x2x3 )G1G5fG4G2xx2x3x1x419Single Path Sensitization (SPS)1. Activate: Specify inputs so as to generate the appropriate value (0 for s-a-1, 1 for s-a-0) at the site of the fault.2. Propagate: Select a path from the site of the fault to an output and specify additional signal values to propagate the fault signal along this path to the output(error propagation).3. Justify; Specify input values so as to produce the signal values specified in (2)(line justification).1020Sensitization Example h s-a-1Activate?f1f2G6G5G4G3G1h s-a-1G2DABCEx21Sensitization Example h s-a-1Activate: To generate h = 0, need A = B = C = 1Propagate?f1f2G6G5G4G3G1hG2DABCEx1122Sensitization Example h s-a-1To generate h = 0, need A = B = C = 1Have a choice of propagating through G5or via G6. Propagating through G5requires G2= 1⇒⇒⇒⇒A = D = 0 ContradictionPropagating through G6requires G4= 1 ⇒⇒⇒⇒C = 1, E = 0.A valid test vector is ABCEf1f2G6G5G4G3G1hG2DABCEx23Line JustificationE s-a-1 ⇒⇒⇒⇒ E = 0C = D = 1 to propagate through G1.To propagate through G4, need G2 = G3= 1How do we justify these values?G31G4G21G1x0s-a-1BHAFCDE1224Line Justification - 2Attempt to line justify G2= G3= 1G3= 1 possible if A = F = 1 or B = H = 1If A = C = 1, then G2= 0. G3= 1 ⇒⇒⇒⇒ B = H = 1G2= 1 needs A = 0 or F = 0 Tests are !ABCD!EH, BCD!E!FHG31G4G21G1x0BHAFCDEs-a-125Existence of a fault does not change the functionality of a circuit ⇒⇒⇒⇒ redundant faultf = x1+ x1x2f = x1+ x2A test generation algorithm is deemed complete if it either finds a test for any fault or proves its redundancy, upon terminating.Redundancyxs-a-1x1x2fx1x2f1326Completeness of SPS method ?d s-a-0 ⇒⇒⇒⇒ A = B = 1Propagate along G3, G6⇒⇒⇒⇒ C = 1G2= G4= G5= 1For G4= 1 either G1= 0 or E = 0If G1= 0 fault is not activiatedIf E = 0 (B must be 1) ⇒⇒⇒⇒ G5= 0 InconsistencyABxds-a-0fG2G6G3G4G5CEG127Completeness of SPS? - 2Propagation along G4, G6also results in inconsistencies by symmetric argumentIs there no test?ABxds-a-0fG2G6G3G4G5CE1428Multiple Path SensitizationError propagates down two paths G3, G6and G4, G6to outputIt’s natural to work backwards (justifying) and forwards (propagating) from point of fault activation but this focuses on sensitizing a single pathAttempting to sensitize a single path will not find a


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