RTN (Register Transfer Notation)RTN Features: Describing Static PropertiesRTN Features: Describing Dynamic Properties Describing the SRC (static) Processor StateRTN Register DeclarationsMemory Declaration:Big-Endian & Little-Endian StorageInstruction Formatting: Renaming of IR BitsREVIEWLoad & Store Inst: Memory AddressingDynamic Address CalculationMemory Address RangesInstr. Interpretation: Fetch/Execute CycleRTN Sequence and ClockingMore about Instruction InterpretationIndividual InstructionsLoad &Store Instruction ExecutionSRC RTN—The Main LoopExample: Load Instruction SemanticsSRC Branch InstructionsRTN for Arithmetic and LogicRTN for Shift InstructionsExp: of Replication & Concatenation in ShiftAssembly Language for ShiftDefinition of instruction_executionThe Relationship of RTN to SRCA Note about Specification LanguagesAddressing Modes Described in RTN But Not Necessarily Implemented in SRCRegister transfers  Digital LogicMultiple Bit Register TransferData Transmission View of Logic GatesMultiplexer as a 2 Way Gated Mergem-bit Multiplexer and SymbolSeparating Merged DataMultiplexed Reg Transfers with Gates & StrobesTri-state Gate Internal Structure & SymbolRegisters Connected by a Tri-state BusRegisters & Arithmetic Connected by One BusTiming of the Register TransfersRT’s Possible with the One Bus StructureAbstract RTN  Concrete RTN  Control Sequences  Data Path & Control DesignChapter 2 SummaryComputer Systems Design and Architecture 2ndEdition © 2004 Prentice Hall, Mark Franklin S06RTN (Register Transfer Notation) A formal means of describing machine structure & function. Is at the “just right” level for machine descriptions. Does not replace hardware description languages.  RTN is approximately a level above VHDL Can be used to describe what a machine does without describing how the machine does it. Can also be used to describe a particular hardware implementation (A Concrete RTN).Computer Systems Design and Architecture 2ndEdition © 2004 Prentice Hall, Mark Franklin S06RTN Features: Describing Static PropertiesStatic Properties Specifying registers: IR〈31..0〉: a register named “IR” having 32 bits numbered 31 to 0 “Naming” using the := naming operator: op〈4..0〉 := IR〈31..27〉 specifies that the 5 msbs of IR be called op, with bits 4..0. This does not create a new register, it just generates a new “alias” for an existing register or part of a register.Computer Systems Design and Architecture 2ndEdition © 2004 Prentice Hall, Mark Franklin S06RTN Features: Describing Dynamic PropertiesDynamic Properties• Conditional expressions:(op=12) → R[ra] ← R[rb] + R[rc]: ; defines the add instruction“if” condition “then” RTN Assignment OperatorSRC add instruction (above): “when the op field of IR = 12, then store in the register specified by the ra field, the result of adding the register specified by the rb field to the register specified by the rc field.”Computer Systems Design and Architecture 2ndEdition © 2004 Prentice Hall, Mark Franklin S06Describing the SRC (static) Processor StateProcessor statePC〈31..0〉: program counter (memory addr. of next inst.)IR〈31..0〉: instruction registerRun: one bit run/halt indicatorStrt: start signal (set on power up and initialization)R[0..31]〈31..0〉: general purpose registersOther state registers defined later.Computer Systems Design and Architecture 2ndEdition © 2004 Prentice Hall, Mark Franklin S06RTN Register Declarations General register specification  Describes a set of 32, 32-bit registers with names R[0] to R[31]R[0..31]〈31..0〉:Name ofregistersRegister #in squarebrackets.. specifiesa range ofindicesmsb #lsb#Bit # inanglebracketsColon separatesstatements withno orderingComputer Systems Design and Architecture 2ndEdition © 2004 Prentice Hall, Mark Franklin S06Memory Declaration:Main memory state & Memory wordMem[0..232-1]〈7..0〉:232addressable bytes of memoryM[x]〈31..0〉 := Mem[x]#Mem[x+1]#Mem[x+2]#Mem[x+3]:DummyparameterNamingoperatorConcatenationoperatorAll bits inregister if nobit index givenComputer Systems Design and Architecture 2ndEdition © 2004 Prentice Hall, Mark Franklin S06Big-Endian & Little-Endian StorageWhen data types having a word size larger than the smallestaddressable unit are stored in memory the question arises,“Is the least significant part of the word stored at thelowest address (little Endian, little end first) or–is the most significant part of the word stored at thelowest address (big Endian, big end first)”?CPU Word bit locations b31 … b24 b23 … b16 b15 … b8 b7 … b0Big-endian byte addr. 0 1 2 3Little-endian byte addr. 3 2 1 00 b7 … b01 b15 … b82 b23 … b163 b31 … b24……0 b31 … b241 b23 … b162 b15 … b83 b7 … b0……Little endianBig endianComputer Systems Design and Architecture 2ndEdition © 2004 Prentice Hall, Mark Franklin S06Instruction Formatting: Renaming of IR BitsInstruction formatsop〈4..0〉 := IR〈31..27〉: operation code fieldra〈4..0〉 := IR〈26..22〉: target register fieldrb〈4..0〉 := IR〈21..17〉: operand, address index, orbranch target registerrc〈4..0〉 := IR〈16..12〉: second operand, conditionaltest, or shift count registerc1〈21..0〉 := IR〈21..0〉: long displacement fieldc2〈16..0〉 := IR〈16..0〉: short displacement orimmediate fieldc3〈11..0〉 := IR〈11..0〉: count or modifier fieldComputer Systems Design and Architecture 2ndEdition © 2004 Prentice Hall, Mark Franklin S06REVIEWLoad & Store Inst: Memory Addressing Address: constant, constant+register, or constant+PC Memory contents or address itself can be loadedInstruction op ra rb c1 Meaning Addressing Modeldr1,32 11032R[1]←M[32]Directld r22, 24(r4) 1 22 4 24R[22]←M[24+R[4]]Displacementst r4, 0(r9) 3 4 9 0M[R[9]]←R[4]Register indirectlar7,32 57032R[7]←32Immediateldr r12, -48 2 12 – -48R[12]←M[PC -48]Relativelarr3,0 63–0R[3]←PCRegister (!)(note use of la to load a constant)Computer Systems Design and Architecture 2ndEdition © 2004 Prentice Hall, Mark Franklin S06Dynamic