RTN Register Transfer Notation A formal means of describing machine structure function Is at the just right level for machine descriptions Does not replace hardware description languages RTN is approximately a level above VHDL Can be used to describe what a machine does without describing how the machine does it Can also be used to describe a particular hardware implementation A Concrete RTN Computer Systems Design and Architecture 2nd Edition 2004 Prentice Hall Mark Franklin S06 RTN Features Describing Static Properties Static Properties Specifying registers IR 31 0 a register named IR having 32 bits numbered 31 to 0 Naming using the naming operator op 4 0 IR 31 27 specifies that the 5 msbs of IR be called op with bits 4 0 This does not create a new register it just generates a new alias for an existing register or part of a register Computer Systems Design and Architecture 2nd Edition 2004 Prentice Hall Mark Franklin S06 RTN Features Describing Dynamic Properties Dynamic Properties Conditional expressions op 12 R ra R rb R rc if condition then defines the add instruction RTN Assignment Operator SRC add instruction above when the op field of IR 12 then store in the register specified by the ra field the result of adding the register specified by the rb field to the register specified by the rc field Computer Systems Design and Architecture 2nd Edition 2004 Prentice Hall Mark Franklin S06 Describing the SRC static Processor State Processor state PC 31 0 program counter memory addr of next inst IR 31 0 instruction register Run one bit run halt indicator Strt start signal set on power up and initialization R 0 31 31 0 general purpose registers Other state registers defined later Computer Systems Design and Architecture 2nd Edition 2004 Prentice Hall Mark Franklin S06 RTN Register Declarations General register specification Describes a set of 32 32 bit registers with names R 0 to R 31 R 0 31 31 0 Name of registers Register in square brackets msb specifies a range of indices Computer Systems Design and Architecture 2nd Edition lsb Colon separates statements with no ordering Bit in angle brackets 2004 Prentice Hall Mark Franklin S06 Memory Declaration Main memory state Memory word Mem 0 232 1 7 0 232 addressable bytes of memory M x 31 0 Mem x Mem x 1 Mem x 2 Mem x 3 Dummy parameter Naming operator Computer Systems Design and Architecture 2nd Edition Concatenation operator All bits in register if no bit index given 2004 Prentice Hall Mark Franklin S06 Big Endian Little Endian Storage When data types having a word size larger than the smallest addressable unit are stored in memory the question arises Is the least significant part of the word stored at the lowest address little Endian little end first or is the most significant part of the word stored at the lowest address big Endian big end first CPU Word bit locations b31 b24 b23 b16 b15 b8 b7 b0 Big endian byte addr 0 1 2 3 Little endian byte addr 3 2 1 0 Little endian 0 b7 b0 0 b31 b24 1 b15 b8 1 b23 b16 2 b23 b16 2 b15 b8 3 b31 b24 3 b7 b0 Big endian Computer Systems Design and Architecture 2nd Edition 2004 Prentice Hall Mark Franklin S06 Instruction Formatting Renaming of IR Bits Instruction formats op 4 0 IR 31 27 ra 4 0 IR 26 22 rb 4 0 IR 21 17 rc 4 0 IR 16 12 c1 21 0 IR 21 0 c2 16 0 IR 16 0 c3 11 0 IR 11 0 Computer Systems Design and Architecture 2nd Edition operation code field target register field operand address index or branch target register second operand conditional test or shift count register long displacement field short displacement or immediate field count or modifier field 2004 Prentice Hall Mark Franklin S06 REVIEW Load Store Inst Memory Addressing Address constant constant register or constant PC Memory contents or address itself can be loaded Instruction ld r1 32 ld r22 24 r4 st r4 0 r9 la r7 32 ldr r12 48 lar r3 0 op 1 1 3 5 2 6 ra 1 22 4 7 12 3 rb 0 4 9 0 c1 32 24 0 32 48 0 Meaning R 1 M 32 R 22 M 24 R 4 M R 9 R 4 R 7 32 R 12 M PC 48 R 3 PC Addressing Mode Direct Displacement Register indirect Immediate Relative Register note use of la to load a constant Computer Systems Design and Architecture 2nd Edition 2004 Prentice Hall Mark Franklin S06 Dynamic Address Calculation Determining the Effective address occurs at runtime Displacement effective address calculation Direct or Absolute address calculation disp 31 0 rb 0 c2 16 0 sign extend rb 0 R rb c2 16 0 sign extend 2 s comp Relative address calculation rel 31 0 PC 31 0 c1 21 0 sign extend 2 s comp Note Register R 0 cannot be added to a displacement Computer Systems Design and Architecture 2nd Edition 2004 Prentice Hall Mark Franklin S06 Memory Address Ranges Memory address range for direct addressing disp rb 0 Memory address range for relative addressing If c2 16 0 positive displacement absolute addresses range from 00000000H to 0000FFFFH If c2 16 1 negative displacement absolute addresses range from FFFF0000H to FFFFFFFFH The largest positive value of C1 21 0 is 221 1 and its most negative value is 221 so addresses up to 221 1 forward and 221 backward from the current PC value can be specified Note the difference between rb and R rb Computer Systems Design and Architecture 2nd Edition 2004 Prentice Hall Mark Franklin S06 Instr Interpretation Fetch Execute Cycle Need to describe actions not just declarations Some new notation Logical NOT Logical AND instruction interpretation Run Strt Run 1 Run IR M PC PC PC 4 instruction execution Register transfer Separates actions that are sequential Separates actions that are concurrent Computer Systems Design and Architecture 2nd Edition 2004 Prentice Hall Mark Franklin S06 RTN Sequence and Clocking In general RTN statements separated by take place during the same clock pulse Statements separated by take place on successive clock pulses This is not entirely accurate since some things written with one RTN statement can take several clocks to perform More precise difference between and The order of execution of statements separated by does not matter If statements are separated by the one on the left must be complete before the one on the right starts i e precedence must be preserved Computer Systems Design and Architecture 2nd Edition 2004 Prentice Hall Mark Franklin S06 More about Instruction Interpretation In the expression IR M PC PC PC 4 which value of PC applies to M PC The rule in RTN is that all right hand sides of separated RTs are evaluated before any LHS is changed We see what happens when Run is true and when