CS, CoE, EE 362 Digital Computers II: ArchitectureFour Key QuestionsEssential Computer ComponentsArchitecture ComponentsSlide 5Performance Expression: Amdahl’s LawAmdahl’s LawGeneralize Amdahl’s LawComputer Market Partitioning (costs are for processor, not system)HLL (e.g., C, C++, Perl) vs Machine/Assembly Language (AL)Example: HLL  AL MappingBuses: IBuses: IIBandwidth RequirementsBandwidth TrendSimple Queuing Theory View of BusesBasic Queueing TheoryBasic Queueing ResultsSlide 19Computer GenerationsTechnology: How we make a chip (roughly)Integrated Circuit CostTECHNOLOGY TRENDSSlide 24Slide 25SILICON & MAGNETIC DENSITIESProcessor Performance GainsSlide 28Slide 29Mark Franklin, S06CS, CoE, EE 362Digital Computers II: Architecture•Prof. Mark Franklin: [email protected]•Course Assistants: –Drew Frank: [email protected]•Required Book: “Heuring & Jordan” 2nd Edition•Optional Book: “Intro. VHDL” Yalamanchili •Read: Academic Integrity Statement.•Course Web Site: http://www.cse.wustl.edu/~jbf/cse362.d/cse362.htmlMark Franklin, S06Four Key Questions•What components must every computer have ?•How can computers be described, specified and evaluated ?•What constitutes computer architecture (hardware, software, firmware, algorithms, etc.) ?•How does technology effect computer architecture (chip size, feature size, power, pin density, etc) ?Mark Franklin, S06Essential Computer Components•Processor: interpret/execute instructions.•Memory: store instructions & data.•Communication Device(s): communicate with outside world, I/O.ProcessorControlUnitALUMemoryInput/OutputClassic Computer Architecture (SISD: Single Instruction Stream-Single Data Stream)Mark Franklin, S06Architecture Components• INSTRUCTION SET DESIGN: Programmer visible instruction set Algorithm, compiler, OS design, algorithmic complexity• HIGH LEVEL COMPONENT ORGANIZATION: Memory system, bus structure, processor design, branch handling, pipelining, execution algorithms, instructions/second, clocks/instruction.• HARDWARE: Detailed logic design, packaging VLSI & Logic design CAD algorithms speed, area, power, …Mark Franklin, S06ALU ALUALUALUInterconnection NetworkData Memory UnitProgram Control UnitProgramMemoryInput / Output(SIMD) Single Instruction Stream – Multiple Data Stream ArchitectureMark Franklin, S06Performance Expression: Amdahl’s Law / Efficiency present processors ofnumber /)1(1speedup eachieveabl maximum10;lysequential performedbemustthatoperationsoffractionpSEppffSSffnnnnMark Franklin, S06Amdahl’s LawIt does no good to have many processors if there is notenough parallelism. What portion of a computation can be sequential if we want the processors to be used at 50 percent efficiency ? ( S = p/2 ).processors of number theof inverse the toalproportion bemust processing sequential todevotedn computatio the offraction the,efficiencyconstant amaintain To1121/)1(12/pffpfpffpnnnnnMark Franklin, S06Generalize Amdahl’s LawSpeedupoverall =ExTimeoldExTimenew=1(1 - Fractionenhanced) + FractionenhancedSpeedupenhancedExample: “Suppose a program runs in 100 seconds on a machine. Multiply operations are responsible for 80 seconds of this time. How much do we have to improve the speed of multiplication if we want the program to run 4 times faster?”What about 5 times faster?PRINCIPAL: Make the common case fast!Mark Franklin, S06Computer Market Partitioning(costs are for processor, not system)•Desktop Computing ($100 - $1,000):–Price-performance•Servers: ($200 - $2,000)–Availability (reliability + effectiveness)–Scalability–Throughput•Embedded Computers: ($0.20 - $1,000)–Real-time performance–Power and memory minimization–Cost minimization–Interface with special purpose logic; use of processor coresMark Franklin, S06HLL (e.g., C, C++, Perl) vs Machine/Assembly Language (AL)•HLL Pros: –Easier to express algorithms due to higher level constructs (e.g., For, Case, Arithmetic expressions, objects, etc.)–Type checking (Hardware for type checking ?).–Some memory allocation checking.•Assembly Language Pros:–More control over ISA  more speed, less memory–More control over I/O•Combination is often best for embedded systems: HLL calling AL .Mark Franklin, S06Example: HLL  AL Mapping•b = c + d*e•LOAD R1, d•LOAD R2, e•LOAD R3, c•MPY R4, R2, R1•ADD R5, R4, R3•STORE R5, bHLLALMark Franklin, S06Buses: I•A set of path(s) (wires) connecting on-chip or off-chip modules. –Serial bus: transmit one bit at a time–Parallel bus: transmits many bits simultaneously •Generally time-shared.•Generally has separate data & control paths.•Typically has a separate bus controller or arbiter that decides which modules can use the bus at any given time.Mark Franklin, S06Buses: II•Some common buses: –On-chip: AMBA, Wishbone, (generally not standard)–Off-chip: PCI Bus Family), •---------------- 32bit transfer 64bit transfer•33-MHz PCI 133 MB/sec 266 MB/sec•66-MHz PCI 266 MB/sec 532 MB/sec•100-MHz PCI-X ------------ 800 MB/sec•133-MHz PCI-X ------------ 1 GB/sec•PCI-e(xpress) serial, 1 lane 500 MB/sec•PCI-e(xpress) serial, 4 lanes 2 GB/sec–Off-chip: Other buses - SCSI, IDE, Infiniband•Common issues: Arbitration, congestion.•Logical equivalence between buses, multiplexers and switches.Mark Franklin, S06Bandwidth RequirementsMark Franklin, S06Bandwidth TrendMark Franklin, S06Simple Queuing Theory View of Buses• Bus is a shared resource and can be viewed as a server in a queuing system.• Modules attached to the bus present inputs (i.e., requests) to the server (or Bus) and are queued up if the server is busy.BUSCPUI/OMemoryServerQueueMark Franklin, S06Basic Queueing Theory•Utilization: % time a server is busy•Average Queue Length: Avg # of jobs in queue.•Average System Delay (latency): Avg time from job entry into, to job departure from system.•Arrival Time Distribution: Poisson Distribution of arrival times (exponential interarrival times).•Service Time Distribution: Exponentially distributed service times.•Queue Charactericstics: Infinite length; FIFO service discipline.Mark Franklin, S06Basic Queueing