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WUSTL CSE 362M - Chapter 5 Overview

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Chapter 5 (b) OverviewInstruction Dependence & Pipeline HazardsGeneral Data Hazard ClassificationGeneral Data Hazard Classification (cont)Detecting Data Hazards & Dependence DistanceData Hazards in SRCDealing with Register Data HazardsRAW Hazard Distance AnalysisInstruction Pair Hazard InteractionRAW Delays Unavoidable by ForwardingStalling the Pipeline on Hazard DetectionStalls Due to a Dependence Between Two ALU InstructionsDetecting ALU Hazards &Stalling PipelineData Forwarding: From ALU Instruction to ALU InstructionData Forwarding: ALU to ALU Instruction (continued)ALU to ALU Data Forwarding Hardware Branch InstructionsHazards Due to Branch InstructionsThe Branch Delay SlotInstruction Level ParallelismFunction Units in Multiple Issue MachinesSimple Branch Prediction Algorithm (Doesn’t Apply to SRC, useful in many stage pipeline)Barrel Shifter with a Logarithmic Number of StagesA 6 Bit Crossbar Barrel Rotator for Fast ShiftingProperties of the Crossbar Barrel ShifterDual Issue VLIW version of SRCStructure of the Dual-Pipeline SRCOther featuresSRC Programs to Compute the Fibonacci Series on Single- and Dual-issue machinesFibonacci Program on Dual-Issue MachineDual-Issue SRC Pipelines & Forwarding PathsDynamic Information in Dual-Issue SRCOperand Flow of st r8, 4(r7)Some Commercial Superscalar ProcessorsMicroprogramming: Basic IdeaControl Sequence: SRC shr InstructionSimplified MicroProgrammed MachineThe Microcode EngineBlock Diagram of a µcoded Control Unitµprogrammed Control Unit ComponentsContents of a MicroinstructionLayout of the Control StoreSize & Shape of System RAM vs Control Storeµinst Control Signals for add InstructionUses for branching in the Microprogrammed Control UnitIllustration of branching Control LogicBranching Controls in the Microcoded Control UnitSome Possible branches Using the Illustrated LogicHorizontal vs Vertical MicrocodingSaving Control Store Bits: Vertical MicrocodeVertical EncodingCompletely Horizontal & Vertical MicrocodingA µprogrammed Control Unit for the 1-bus SRCMicroinstructions for SRC addGetting the PLA Output in Time for the MicrobranchSee-thru Latch Hardware for IR So PC Can Load ImmediatelyMicrocode Sequencer Logic for SRCA Somewhat Vertical Encoding of the SRC MicroinstructionMore Microprogramming PointsChapter 5 SummaryComp. Sys. Design & Arch. 2nd Edition © 2004 Prentice Hall, Mark Franklin S07Chapter 5 (b) Overview (a)The principles of pipelining (a) A pipelined design of SRC (b)Pipeline hazards (b) Instruction-level parallelism (ILP) Superscalar processors Very Long Instruction Word (VLIW) machines (b) Microprogramming Control store and micro-branching Horizontal and vertical microprogrammingComp. Sys. Design & Arch. 2nd Edition © 2004 Prentice Hall, Mark Franklin S07Instruction Dependence & Pipeline Hazards Instructions that occupy the pipeline together are being executed in parallel This leads to the problem of instruction dependence.  The basic problem is that an instruction depends on the result of a previously issued instruction that is not yet complete, or an instruction requires a resource used by another instruction in the pipeline. Three categories of hazards: Resource hazards: not enough hardware to perform parallel operations (e.g., single ALU for PC ÅPC+4, & for ALU instructions. Data hazards: incorrect use of old and new data Branch hazards: fetch of wrong instruction on a change in PCComp. Sys. Design & Arch. 2nd Edition © 2004 Prentice Hall, Mark Franklin S07General Data Hazard Classification A read after write hazard (RAW) arises from a flow dependence, where an instruction uses data produced by a prior instruction, but the data is not ready.add r0, r2, r4sub r3, r0, r1 --- sub fetches r0 before add has updated its value. A write after read hazard (WAR) comes from an anti-dependence, where an instruction writes a new value over one that is still needed by a previous instruction.add r2, r1, r0sub r0, r3, r4 ---if add & sub executed in parallel or out-of-order and ---you could not guarantee that add completed prior to sub,---then one could get a WAR hazard. Not possible on SRC.Comp. Sys. Design & Arch. 2nd Edition © 2004 Prentice Hall, Mark Franklin S07General Data Hazard Classification (cont) A write after write hazard (WAW) comes from an output dependence, where two parallel instructions write the same register and must do it in the order in which they were issued.add r0, r1, r2sub r0, r4, r5 ---If add & sub are executed in parallel or out of ---order, then output register can be overwritten --- by add instruction. Not possible on SRC.WAW and WAR can sometimes be fixed by “register renaming” and synchronization. Rename r0 in the add to rx. Then:add rx, r1, r2sub r0, r4, r5 ---r0 cannot now be overwritten by add even if ---they are performed out-of-order.Comp. Sys. Design & Arch. 2nd Edition © 2004 Prentice Hall, Mark Franklin S07Detecting Data Hazards & Dependence Distance To detect hazards, pairs of instructions must be considered. Data is normally available after being written to register. Can be made available for forwarding as early as the stage where it is produced. Stage 3 output for ALU results, stage 4 for memory fetch. Operands normally needed in stage 2. Can be received from forwarding as late as the stage in which they are used. Stage 3 for ALU operands and address modifiers, stage 4 for stored register, stage 2 for branch target.Comp. Sys. Design & Arch. 2nd Edition © 2004 Prentice Hall, Mark Franklin S07Data Hazards in SRC Since all data memory access occurs in stage 4, memory writes & reads are sequential & give rise to no hazards. Since all registers are written in the last stage, WAW & WAR hazards do not occur. Two writes always occur in the order issued, and a write always follows a previously issued read. SRC hazards on register data are limited to RAW hazards coming from flow dependence (i.e., Values are written into registers at the end of stage 5 but may be needed by a following instruction at the beginning of stage 2.)Comp. Sys. Design & Arch. 2nd Edition © 2004 Prentice Hall, Mark Franklin S07Dealing with Register Data Hazards Detection: The machine manual could list rules specifying that a dependent instruction cannot be issued less than a given number of steps after the one on which it depends Æ too


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