Chapter 7 The Memory Hierarchy Part I The slides of Part I are taken in large part from V Heuring H Jordan Computer Systems Design and Architecture SP06 Mark Franklin 1 Memory Hierarchy Outline 1 Memory components RAM memory cells cell arrays Static RAM more expensive but less complex Tree and matrix decoders needed for large RAM chips Dynamic RAM less expensive but needs refreshing Chip organization Timing ROM Read only memory Memory boards Arrays of chips give more addresses and or wider words 2 D and 3 D chip arrays Memory modules Large systems can benefit by partitioning memory for separate access by system components fast access to multiple words SP06 Mark Franklin 2 Memory Hierarchy Outline 2 The Memory Hierarchy from fast expensive to slow cheap Registers Cache Main Memory Disk Consider two adjacent hierarchy levels Cache Main Memory Cache High speed expensive 1st level on chip 2nd level off chip Design Types Direct mapped associative set associative Virtual memory Makes the hierarchy to disk transparent Translate the address from CPU s logical address to the physical address where the information is actually stored Memory management how to move information back and forth Multiprogramming multithreading what to do while we wait The TLB helps in speeding the address translation process Memory as a subsystem Overall performance SP06 Mark Franklin 3 Memory Technology Characteristics Level Memory Type Average Access Time Typical Size Unit of Transfer Block Size Word 16 64bits Cache line 8B 32B 1 Cache 25 10ns 8KB 32MB 2 Main Memory 40 200ns 2MB 32GB 3 Disk 5 10ms 100Gb Page 4KB 16KB 4 Magnetic Tape 1 5sec 200Gb Record 16KB SP06 Mark Franklin 4 Memory Performance Gap Processor DRAM Memory Gap latency Proc 60 yr Moore s Law 2X 1 5yr Processor Memory Performance Gap grows 50 year DRAM DRAM 9 yr 2X 10 yrs Performance 1000 CPU 100 10 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 1 Time SP06 Mark Franklin 5 Levels of the Memory Hierarchy Capacity Access Time Cost CPU Registers 100s Bytes 2s ns Cache 100s K Bytes 3 2 ns 1 0 1 cents bit Staging Xfer Unit Registers Instr Operands Disk 100sG Bytes 10 ms 10 6 10 7 cents bit Tape infinite sec min 10 8 cents bit SP06 Mark Franklin faster prog compiler 1 8 bytes Cache Blocks Main Memory 1000s M Bytes 100ns 400ns 0001 00001 cents bit Upper Level cache 8 128 bytes Memory Pages OS 512 8K bytes Files user operator Mbytes Disk Tape Larger Lower Level 6 The CPU Memory Interface Sequence of events Read 1 CPU loads MAR issues Read REQUEST 2 Main memory transmits words to MDR 3 Main memory asserts COMPLETE Data bus Address bus CPU M ain memory m s m A0 A m 1 MAR w Address 0 1 b D0 Db 1 MDR 2 w 3 R W Write 1 CPU loads MAR MDR asserts Write REQUEST 2 MDR MAR 3 Main memory asserts COMPLETE SP06 Mark Franklin Register file REQUEST 2m 1 CO MPLETE Control signals 7 The CPU Memory Interface cont d Data bus Address bus CPU m MAR Main memory s m A0 Am 1 w MDR Address 0 1 b D0 Db 1 2 3 w R W Register file REQUEST 2m 1 COMPLETE Control signals Additional points If b w main memory must make w b b bit transfers Some CPUs allow reading writing of word sizes w Exp Intel 8088 m 20 8 and 16 bit values can be read written If memory is sufficiently fast or if its response is predictable then COMPLETE may be omitted Some systems use separate R W lines omit REQUEST SP06 Mark Franklin 8 Memory Performance Parameters Symbol Definition Units Meaning ta Access timetime Time to access a memory word tc Cycle time time Time from start of access to start of next access k Block size words Number of words per block Bandwidth words time Word transmission rate tl Latency time Time to access first word of a sequence of words tbl Block time Time to access an entire block of words tl k access time Information is stored moved in blocks at the cache disk level SP06 Mark Franklin 9 Memories Basic Technologies SRAM value is stored on a pair of inverting gates very fast but takes up more space than DRAM 4 to 6 transistors Cross Coupled gates more later DRAM value is stored as a charge on capacitor must be refreshed very small hence higher density but slower than SRAM factor of 5 to 10 Wordline Passtransistor Capacitor Bit line SP06 Mark Franklin 10 Memory Cell Structure Regardless of the technology all RAM memory cells must provide these four functions Select DataIn DataOut and R W Select DataIn DataOut R W SP06 Mark Franklin 11 An 8 Bit Register as a 1 D RAM Array The entire register is selected with one select line and uses one R W line Select DataIn D DataOut R W Select D D D D D D D D d0 d1 d2 d3 d4 d5 d6 d7 R W Data bus is bidirectional and buffered SP06 Mark Franklin 12 A 4 x 8 2 D Memory Cell Array 2 4 line decoder selects one of the four 8 bit arrays 2 bit address 2 4 decoder A1 D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D d0 d1 d2 d3 d4 d5 d6 d7 A0 R W R W is common to all Bidirectional 8 bit buffered data bus SP06 Mark Franklin 13 A 64 K x 1 Static RAM Chip square array fits IC design paradigm Row address A0 A7 8 Selecting rows separately from columns means only 256 x 2 512 circuit elements instead of 65536 circuit elements 8 256 row decoder 256 256 256 cell array 256 Column address A8 A15 CS Chip Select allows chips in arrays to be selected individually R W CS 8 1 256 1 mux 1 1 256 demux Data Input 1 output This chip requires 21 pins including power and ground and so will fit in a 22 pin package SP06 Mark Franklin 14 A 16 K x 4 SRAM Chip Row address A0 A7 8 8 256 row decoder There is little difference between this chip the previous one except that there are 4 64 1 muxes instead of 1 256 1 mux Output is 4 words 256 4 64 256 cell arrays 64 each Column address A8 A13 R W 6 4 64 1 muxes 4 1 64 demuxes 4 Data Input output CS This chip requires 24 pins including power and ground and so will require a 24 pin package Package size and pin count can dominate chip cost SP06 Mark Franklin 15 Matrix Tree Decoders 2 level decoders are limited in size because of gate fan in fan in 8 Decoders built with fan in 8 require additional gate levels When fan in 8 tree matrix …