Goals Understanding Structure Function of Digital Computer Multiple levels of computer operation This course Interactions and relations between levels This course Application level High Level Language s HLL level s Assembly machine language level instruction set System architecture level subsystems connections Digital logic level gates memory elements buses Electronic design level Semiconductor physics level View of machine at each level Tasks and tools at each level Historical perspective Trends and research activities Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 Scales Units and Conventions Term Normal Usage K kilo 10 3 M mega 10 6 G giga T tera 10 9 10 12 Term Usage m milli micro n nano p pico 10 3 10 6 10 9 10 12 Exp Memories As a power of 2 2 10 1024 2 20 1 048 576 2 30 1 073 741 824 bits register file 2 40 1 099 511 627 776 bytes disk array bytes memory bytes disk Exp Timing disk latency ms off chip memory access s on chip clock period ns gate delay ps e g 100ps Units Bit b Byte B Nibble Word w Double Word Long Word Second s Hertz Hz Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 Machine assembly Language Programmer s View Machine language Assembly language Set of fundamental instructions the machine can execute A pattern of 1 s and 0 s Alphanumeric equivalent of machine language Mnemonics more human oriented than 1 s and 0 s Assembler A program that translates assembly to machine language Computer s native language is assembly machine language Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 Machine and Assembly Language Assembly Language Program ASSEMBLER Op code Machine Language Program Data reg 5 Data reg 4 Two Motorola MC68000 instructions MC68000 Assembly Language Machine Language MOVE W D4 D5 0011 101 000 000 100 ADDI W 9 D2 add opcode 16b Reg Imm data 00000110 01 000 010 0000 0000 0000 1001 Size of imm data Computer Systems Design Architecture 2nd Edition 2 Mode reg 1 1 2004 Prentice Hall Mark Franklin Fall 06 The Fetch Execute Cycle Register File Program Counter Instruction Register Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 AL Programmer s World View Instruction Set Architecture ISA Instruction set the collection of all machine operations Programmer s View sees set of instructions along with the machine resources manipulated by them ISA includes instruction set memory and programmer accessible registers of the system There may be memory or other resources used to implement some functions that are not part of ISA and are thus Non Programmer Accessible Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 Programmer s Models of 4 commercial machines Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 Machine Processor and Memory State The Machine State contents of all registers in system accessible to programmer or not The Processor State registers internal to the CPU The Memory State register contents in memory system State is used in the formal finite state machine sense Maintaining restoring machine processor state Important to many operations especially procedure calls interrupts Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 HLL vs Assembly Language What capabilities are present not present in HLL versus AL Under what circumstances will you choose one or the other Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 Who Uses Assembly Language The machine designer The compiler writer must implement and trade off instruction functionality must generate machine language from a HLL Applications where performance time space is critical Special purpose or embedded processor programmers Special functions and heavy dependence on unique I O devices can make HLL s useless Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 Assembly Language Programming Tools The assembler The linker The debugger or monitor The development system Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 The Computer Architect s View Architect Concerned with design performance cost ISA designed for optimum programming utility best instruction set performance of implementation To see goals are met architect uses performance measurement tools e g benchmark programs simulation tools e g SimpleScalar analytic modeling tools e g Queuing Theory Balances performance of building blocks such as CPU memory I O devices and interconnections Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 The Memory Hierarchy Modern computers have a hierarchy of memories Allows tradeoffs of speed cost volatility size etc CPU sees common view of levels of the hierarchy Level 1 Cache CPU Cache Memory Main Memory SRAM or DRAM Static Dynamic Random Access Memory Disk Memory Tape Memory Single Chip Level 2 Cache KEY CONCEPT Principal of Locality Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 Logic Designer s View Designs the machine at the logic gate level The design determines whether the architect meets cost and performance goals Architect and logic designer often work as a team Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 Implementation Domains An implementation domain is the collection of devices logic levels etc which the designer uses Possible implementation domains VLSI on silicon current TTL or ECL chips not normally used Gallium Arsenide chips sometimes used in high speed com PLA s or sea of gates arrays current Fluidic logic or optical switches optical switchs work in progress Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 Three Different Implementation Domains 2 to 1 multiplexer in three different implementation domains generic logic gates abstract domain National Semiconductor FAST Advanced Schottky TTL vlsi on Si Fiber optic directional coupler switch optical signals in LiNbO3 Computer Systems Design Architecture 2nd Edition 2004 Prentice Hall Mark Franklin Fall 06 Distinction Btw Classical Logic Design Computer Logic Design The entire computer is too complex for traditional FSM design techniques There is a natural separation between data control