Array Structured MemoriesMemory ArraysFeature Comparison Between Memory TypesArray ArchitectureMemory - Real OrganizationHierarchical Memory ArchitectureArray Organization Design IssuesSimple 4x4 SRAM MemorySRAM Read Timing (typical)Slide 10SRAM Architecture and Read TimingsSRAM write cycle timingSRAM Architecture and Write TimingsSRAM Cell DesignAnatomy of the SRAM CellSRAM Cell Operating PrincipleBistable ElementCell Static Noise MarginSNM: Butterfly CurvesSNM for Poly Load Cell12T SRAM Cell6T SRAM CellSRAM DesignPowerPoint PresentationSRAM Bitcell DesignDetailed SRAM Bitcell LayoutSRAM ReadSlide 28SRAM WriteSRAM SizingSRAM Column ExampleDecodersSingle Pass-Gate MuxDecoder LayoutLarge DecodersPredecodingSlide 37Column CircuitryColumn MultiplexingTypical Column AccessPass Transistor Based Column DecoderTree Decoder MuxEx: 2-way Muxed SRAMBitline ConditioningSense Amplifier: Why?Sense AmplifiersDifferential Pair AmpClocked Sense AmpSense Amp WaveformsWrite Driver CircuitsDual-Ported SRAMMultiple PortsMulti-Ported SRAMLogical effort of RAMsSlide 55Twisted BitlinesAlternative SRAM Cells10TSlide 59Slide 609TSlide 628TSlide 647TSlide 66Slide 676T5TExample Electrical Design: UCSD 32nm prototypeButterfly and N-CurvesIread, Ileakage and VDDHOLDCorner Simulation: Butterfly and N-CurveCorner Simulation: Iread , Ileakage and VDDHOLDEE1411MemorySTMicro/Intel/UCSD/THNUArray Structured MemoriesSTMicro/IntelUCSD CAD LABWeste TextEE1412MemorySTMicro/Intel/UCSD/THNUMemory ArraysMemory ArraysMemory ArraysRandom Access Memory Serial Access MemoryContent Addressable Memory(CAM)Read/Write Memory(RAM)(Volatile)Read Only Memory(ROM)(Nonvolatile)Static RAM(SRAM)Dynamic RAM(DRAM)Shift Registers QueuesFirst InFirst Out(FIFO)Last InFirst Out(LIFO)Serial InParallel Out(SIPO)Parallel InSerial Out(PISO)Mask ROMProgrammableROM(PROM)ErasableProgrammableROM(EPROM)ElectricallyErasableProgrammableROM(EEPROM)Flash ROMEE1413MemorySTMicro/Intel/UCSD/THNUFeature Comparison Between Feature Comparison Between Memory TypesMemory TypesEE1414MemorySTMicro/Intel/UCSD/THNUArray ArchitectureArray Architecture2n words of 2m bits eachIf n >> m, fold by 2k into fewer rows of more columnsGood regularity – easy to designVery high density if good cells are usedrow decodercolumndecodernn-kk2m bitscolumncircuitrybitline conditioningmemory cells:2n-k rows x2m+k columnsbitlineswordlinesEE1415MemorySTMicro/Intel/UCSD/THNUMemory - Real OrganizationMemory - Real OrganizationS0SR-1RowDecoderLog2RAddress Lines- - - - KxM bits - - - -C of M bit words row 0C of M bit words row 1C of M bit words row 2C of M bit words row N-2C of M bit words row N-1Array of N x K words------------- columns ------------ KxM------------- rows R------------Log2CAddress LinesColumn SelectM bit data wordEE1416MemorySTMicro/Intel/UCSD/THNUHierarchical Memory ArchitectureHierarchical Memory ArchitectureGlobal Data BusRowAddressColumnAddressBlockAddressBlock Selector GlobalAmplifier/DriverI/OControlCircuitryAdvantages:1. Shorter wires within blocks2. Block address activates only 1 block => power savingsEE1417MemorySTMicro/Intel/UCSD/THNUArray Organization Design IssuesArray Organization Design Issuesaspect ratio should be relative squareRow / Column organisation (matrix)R = log2(N_rows); C = log2(N_columns)R + C = N (N_address_bits)number of rows should be power of 2number of bits in a row need not be…sense amplifiers to speed voltage swing1 -> 2R row decoder1 -> 2C column decoder M column decoders (M bits, one per bit)–M = output word widthEE1418MemorySTMicro/Intel/UCSD/THNUSimple 4x4 SRAM MemorySimple 4x4 SRAM MemoryA0Row DecoderBLWL[0]A1A2Column Decodersense amplifierswrite circuitry!BLWL[1]WL[2]WL[3]bit line precharge2 bit width: M=2R = 2 => N_rows = 2R = 4C = 1 N_columns = 2c x M = 4N = R + C = 3Array size = N_rows x N_columns = 16clocking and control ->enableread prechargeA0!WE! , OE!EE1419MemorySTMicro/Intel/UCSD/THNUSRAM Read Timing (typical)SRAM Read Timing (typical)tAA (access time for address): time for stable output after a change in address.tACS (access time for chip select): time for stable output after CS is asserted.tOE (output enable time): time for low impedance when OE and CS are both asserted.tOZ (output-disable time): time to high-impedance state when OE or CS are negated.tOH (output-hold time): time data remains valid after a change to the address inputs.EE14110MemorySTMicro/Intel/UCSD/THNUSRAM Read Timing (typical)SRAM Read Timing (typical)stable stable stablevalid valid validtAAtOZ tAAtOEtACStOZtOEMax(tAA, tACS)tOHADDRCS_LOE_LDOUTWE_L = HIGHEE14111MemorySTMicro/Intel/UCSD/THNUSRAM Architecture and Read SRAM Architecture and Read TimingsTimingstAAtACStOEtOZtOHEE14112MemorySTMicro/Intel/UCSD/THNUSRAM write cycle timing SRAM write cycle timing ~WE controlled~CS controlledEE14113MemorySTMicro/Intel/UCSD/THNUSRAM Architecture and Write SRAM Architecture and Write TimingsTimingsWrite drivertWP-tDWSetup time = tDWtDHEE14114MemorySTMicro/Intel/UCSD/THNUSRAM Cell DesignSRAM Cell DesignMemory arrays are largeNeed to optimize cell design for area and performancePeripheral circuits can be complex–60-80% area in array, 20-40% in peripheryClassical Memory cell design6T cell full CMOS 4T cell with high resistance poly loadTFT load cellEE14115MemorySTMicro/Intel/UCSD/THNUAnatomy of the SRAM CellAnatomy of the SRAM CellWrite:•set bit lines to new data value•b’ = ~b•raise word line to “high”•sets cell to new state•Low impedance bit-linesRead:•set bit lines high•set word line high•see which bit line goes low•High impedance bit linesEE14116MemorySTMicro/Intel/UCSD/THNUSRAM Cell Operating PrincipleSRAM Cell Operating Principle•Inverter Amplifies•Negative gain•Slope < –1 in middle•Saturates at ends• Inverter Pair Amplifies•Positive gain•Slope > 1 in middle•Saturates at endsEE14117MemorySTMicro/Intel/UCSD/THNUBistable ElementBistable ElementStabilityRequire Vin = V2Stable at endpointsrecover from pertubationMetastable in middleFall out when perturbedBall on Ramp AnalogyEE14118MemorySTMicro/Intel/UCSD/THNUCell Static Noise MarginCell Static Noise MarginCell state may be disturbed by•DC•Layout pattern offset•Process mismatches •non-uniformity of implantation•gate pattern size errors•AC•Alpha particles•Crosstalk•Voltage supply ripple•Thermal noiseSNM (static