ECE 224a CMOS VLSI Design LabECE 224aClass LogisticsThe First Integrated CircuitsIntel 4004 Micro-ProcessorECE224a ProjectCurrent State of Affairs224a Project LimitsDesign ScheduleSurvival GuideWhat to make?What to NOT make:Design MethodologyEvolution in ComplexityThe Design Productivity ChallengeScaling?The Custom ApproachTransition to Automation and Regular StructuresAutomating DesignA System-on-a-Chip: ExampleSlide 21Implementation ChoicesImplementation Strategies2-d Cell Based: “Hard” Modules1-d Cell-based Design (standard cells)Concepts of PlacementConcepts of RoutingConcept of Routing TracksGrid-Based Routing SystemStandard Cell — Old ExampleStandard Cell – The New GenerationStandard Cell - Example“Soft” MacroModulesGate Array — Sea-of-gatesSea-of-gate Primitive CellsSea-of-gatesThe return of gate arrays?Pre-wired Arrays:Fuse-Based FPGAArray-Based Programmable LogicProgramming a PROMRent’s RuleRent’s Rule:Design FlowDesign Flow - OverviewWhere does the Gate Level Netlist come from?FloorplanningDesign Must Be Floorplanned Before P&RI/O Placement and Chip Package RequirementsGuidelines for a Good FloorplanDefining the Power/Ground Grid and BlockagesDesign Flow – Timing Driven PlacementTiming ConstraintsCell and Net DelaysTiming Driven PlacementLogic OptimizationsThe “Design Closure” ProblemTiming Closure and Mask VerificationDesign Flow – Clock Tree SynthesisAfter Clock Tree SynthesisGated - CTSEffects of CTSTiming Driven RoutingTiming VerificationPhysical VerificationFabricationUCSB ToolsHW 1© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologyECE 224a CMOS VLSI Design LabECE 224a CMOS VLSI Design LabF. Brewer© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologyECE 224aECE 224aFabricate a real designMMI/Cadence/Mentor/Synopsys ToolsMMI Full Custom (Cell, Array, Data-Path)Cadence/Synopsys P&R (digital path)Not a first class in VLSI124a or equivalent required, 124d is good planReview Essential ConceptsFET, Diode, Transient Model (Elmore), SizingLayout/Design Rules: Wire Planning, Gradient Variation, Tricks of Trade© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologyClass LogisticsClass LogisticsHomework (out wed, due 1 week)Quizzes (3 in-class)No FinalDesign ProposalDesign ReviewSubmitted Project Report© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologyThe First Integrated Circuits The First Integrated Circuits Bipolar logic1960’sECL 3-input GateMotorola 1966© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design Methodology Intel 4004 Micro-ProcessorIntel 4004 Micro-Processor19711000 transistors1 MHz operation© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design Methodology0.6um 3M3.3-5V bulk CMOSP1/P2 CAPPoly ResistorHV Implants (up to 40V!)2.25mm21.5mmx1.5mm9 week design cycle, 3 personECE224a ProjectECE224a Project© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologyCurrent State of AffairsCurrent State of AffairsHigh-End Technology (32-22nm) still a driverLimited to large design efforts ($$$NRE)Small number of Players–FPGA: Actel, Lattice, Xilinx, Altera–Processor: AMD, Intel, IBM–SOC: Conexant, Cisco, Juniper, Nintendo…–Structured ASIC: NEC, Fujitsu, Hitatchi, SamsungMost Design Starts > 0.09um!Mixed Signal ApplicationsMature Technology – Lower NRE and RiskHigh Potential for Innovative Design/Architecture© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design Methodology224a Project Limits224a Project LimitsGet 1 1.5x1.5mm design/2-3 students1500 Standard Cell Gates50kbits ROM/5kbits SRAM64 Comparators/ 15 Op-Amps40-48 pins (at least 8 used for Pwr/Gnd)100Mhz practical large swing (3.3V) limit–800+MHz differential 300mV3.3 or 5V default, 12V possible© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologyDesign ScheduleDesign Schedule9 week design flow1 week project definition3 weeks schematic/simulation + test design2 weeks layout2 weeks design verification and tweakTape Out–Must be DRC, LVS Clean–Must have Full Die Simulation/Sanity–Must have test plan and agree to physical test© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologySurvival GuideSurvival GuideChoose Team to Complement Skills!No more than 3. 2 is fine, 1 if enough project slotsUnder-Specify/Over-DeliverIf you cannot finish basic design in 1 week simplify design!Basic Design through layout before adding features!Make decisions early, stick to themUse expert resources: Professors, experienced studentsGoal: Have Fun! --© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologyWhat to make?What to make?Mixed Signal Designs RockPure Digital 1-bit signal processingAnalog Sensors/Digital Output Good Choice–Temperature, Light, Magnetic, RF, Field, voltage, current, time, phase…Digital Synthesis/Power also good–Sound (even music!), RFID/Xmit, motor driver/controller, PLL (clock synthesis or other…), Display (LCD) or LEDTricky Small Designs–Journal of Consumer Circuits, JSSC about 10-15 years ago (0.5um in vogue), LFSR tricks…© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologyWhat to What to NOTNOT make: make:MicroProcessor4-bit possible (8 bit tiny MIPS – won’t fit w/o reg)–1 success in 22 years, 5 months design timeNo non-volatile Memory–(design some is good, but hard, project!)Digital Multiplier/Adder/Function BlockSpace, Pins (How to test!), Why?Generic OpAmpHow to test/characterize?If you have a use in mind – it is not generic!© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologyDesign Design MethodologyMethodology© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologyEvolution in ComplexityEvolution in Complexity© Digital Integrated Circuits2nd and F. Brewer 2003, 2011Design MethodologyThe Design Productivity ChallengeThe Design Productivity ChallengeSource: ITRS’97A growing gap between design complexity and design productivity58%/Yr. compoundComplexity growth rate21%/Yr. compoundProductivity growth rate1981Logic Transistors per Chip (K)Productivity