ECE 224a Process and Design RulesA Modern CMOS ProcessThe Manufacturing ProcessPhoto-Lithographic ProcessPatterning of SiO2CMOS Process Walk-ThroughSlide 7Slide 8Slide 9Advanced Process ModulesLithography for 0.1um NodePoly Gate Etch  100nm12A Gate OxideAdvanced MetallizationInterconnect RC TrendDesign RulesDesign Rules II85nm Poly Gate ProfileCL013 Core Device0.13/0.18 Comparison3D PerspectivePoly-SiGe GateDesign Rules IIICMOS Process Design LayersIntra-Layer Design RulesTransistor LayoutActive Contact IPoly Contact IVia (m1 to m2)Select LayerCMP Density RulesLayout Guidelines IElectromigration (1)Electromigration (2)Metal MigrationLayout Guidelines IIPadsPads-- Chip to Board InterfaceChip PackagingPad FramePad ExampleBus DetailSeal RingSlide 44Chip to Board Interface -- Pad DesignDriving Large CapacitancesUsing Cascaded BuffersOutput Driver DesignDelay as a Function of F and NSlide 50How to Design Large TransistorsBonding Pad DesignESD ProtectionSlide 54PackagingPackaging RequirementsBonding TechniquesTape-Automated Bonding (TAB)Flip-Chip BondingCu Flip-Chip TechnologyPackage-to-Board InterconnectPackage TypesPackage ParametersMulti-Chip ModulesLecture Problems 2EE1411F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingECE 224a ECE 224a Process and Design RulesProcess and Design RulesProcess OverviewDevice Fabrication LimitsDerived LayersSelf Alignment/Dual Damascene/CMPDesign RulesResolution/Step Coverage/ProcessElectrical/Reliability/Mechanical StressEE1412F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingA Modern CMOS ProcessA Modern CMOS Processp-welln-wellp+p-epiSiO2AlCupolyn+SiO2p+gate-oxideTungstenTiSi2Dual-Well Trench-Isolated CMOS ProcessDual-Well Trench-Isolated CMOS ProcessEE1413F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingThe Manufacturing ProcessThe Manufacturing ProcessPhoto-LithographyMask to ResistResist to Pattern LayerProcess (Implant/Etch/Oxide/Nitride/…)Cleanup (Clean/Planarization/Anneal)Setup next Layer for ProcessingFor a great reference source:http://www.reed-electronics.com/semiconductorEE1414F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingoxidationopticalmaskprocessstepphotoresist coatingphotoresistremoval (ashing)spin, rinse, dryacid etchphotoresist stepper exposuredevelopmentTypical operations in a single photolithographic cycle (from [Fullman]).Photo-Lithographic ProcessPhoto-Lithographic ProcessEE1415F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingPatterning of SiO2Patterning of SiO2Si-substrateSi-substrateSi-substrate(a) Silicon base material(b) After oxidation and depositionof negative photoresist(c) Stepper exposurePhotoresistSiO2UV-lightPatternedoptical maskExposed resistSiO2Si-substrateSi-substrateSi-substrateSiO2SiO2(d) After development and etching of resist,chemical or plasma etch of SiO2(e) After etching(f) Final result after removal of resistHardened resistHardened resistChemical or plasmaetchEE1416F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingCMOS Process Walk-ThroughCMOS Process Walk-Throughp+p-epi(a) Base material: p+ substrate with p-epi layerp+(c) After plasma etch of insulatingtrenches using the inverse of the active area maskp+p-epiSiO23SiN4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)EE1417F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingCMOS Process Walk-ThroughCMOS Process Walk-ThroughSiO2(d) After trench filling, CMP planarization, and removal of sacrificial nitride(e) After n-well and VTp adjust implantsn(f) After p-well andVTn adjust implantspEE1418F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingCMOS Process Walk-ThroughCMOS Process Walk-Through(g) After polysilicon depositionand etchpoly(silicon)(h) After n+ source/drain andp+ source/drain implants. Thesep+n+steps also dope the polysilicon.(i) After deposition of SiO2insulator and contact hole etch.SiO2EE1419F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingCMOS Process Walk-ThroughCMOS Process Walk-Through(j) After deposition and patterning of first Al layer.Al(k) After deposition of SiO2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.AlSiO2EE14110F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingGeneration 0.25um 0.18um 0.15um 0.13um 0.1umIsolation STI Substrate Bulk/Epi SOI optionWell Retrograde --> Advanced SSR Gate Dielectric Multiple Gate Dielectric (Core/IO & Mixed-Signal) Gate Dual Poly (n+/p+) Salicide Gate Litho DUV 248nm PSM 193nm PSMJunction Engineering Advanced Junction/Pocket EngineeringSilicide TiSix NiSixBEOL Metal AlAl and Cu Cu BEOL DielectricLow-k (k=3.7) (K<3.0) (K<2.5)CoSix Advanced Process ModulesAdvanced Process ModulesEE14111F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturing80 nm Lines120 nm Contact HolesLithography for 0.1um NodeLithography for 0.1um NodeEE14112F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturing50nmPre-trimTrim X secResist trimming is predictable by computer simulation as well as experiment. Experimental SimulationTrim X+20 secPoly Gate Etch Poly Gate Etch  100nm 100nmEE14113F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturing12A Gate Oxide12A Gate OxideEE14114F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingAdvanced MetallizationAdvanced MetallizationEE14115F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturing0.400.600.801.001.20CL013 CL015 CL018TechnologyNormalized RCCu/Low-k1(Fixed L)Cu/Low-k1(Scaled L)CL013 Cu/Low-k2CL013 Cu/Low-k2Al/Low-k1(Fixed L)Al/Low-k1(Scaled L)Cu/Low-k1Al/Low-k122%15% RC delay is evaluated at minimum M2 pitchInterconnect RC TrendInterconnect RC TrendEE14116F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2ndManufacturingDesign RulesDesign RulesWhat can be fabricated?Resolution Limits–Light Source (357nm, 254nm, 193nm, ?)–Contact/Phase Masking–Surface State (Reflection/Scattering)Material Limits–Step Coverage–Porosity/Defect