Design MethodologyThe Design Productivity ChallengeThe Custom ApproachTransition to Automation and Regular StructuresAutomating DesignA System-on-a-Chip: ExampleSlide 7FloorplanningImplementation ChoicesImpact of Implementation ChoicesImplementation StrategiesPLA: Programmable Logic ArrayTwo-Level LogicPLA Layout – Exploiting RegularityBreathing Some New Life in PLAsExperimental Results2-d Cell Based: “Hard” Modules1-d Cell-based Design (standard cells)Standard Cell — ExampleStandard Cell – The New GenerationStandard Cell - Example“Soft” MacroModulesThe “Design Closure” ProblemGate Array — Sea-of-gatesSea-of-gate Primitive CellsSea-of-gatesThe return of gate arrays?Pre-wired Arrays:Fuse-Based FPGAArray-Based Programmable LogicProgramming a PROM2-input mux as programmable logic blockLogic Cell of Actel Fuse-Based FPGALUT-Based Logic CellArray-Based Programmable WiringMesh-based Interconnect NetworkTransistor Implementation of MeshHierarchical Mesh NetworkAltera MAXAltera MAX Interconnect ArchitectureField-Programmable Gate Arrays Fuse-basedXilinx 4000 Interconnect ArchitectureRAM-based FPGADesign at a crossroad System-on-a-ChipAddressing the Design Complexity Issue Architecture ReuseHeterogeneous Programmable PlatformsSummary© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesDesign Design MethodologyMethodology© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesThe Design Productivity ChallengeThe Design Productivity ChallengeSource: ITRS’97A growing gap between design complexity and design productivity58%/Yr. compoundComplexity growth rate21%/Yr. compoundProductivity growth rate1981Logic Transistors per Chip (K)Productivity (Trans./Staf-Month)1001,00010,000100,0001,000,00010,000,0001001,00010,000100,0001,000,00010,000,000100,000,000101985198919931997200120052009© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesThe Custom Approach The Custom Approach Intel 4004Courtesy Intel© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesTransition to Automation and Regular StructuresTransition to Automation and Regular StructuresIntel 4004 (‘71)Intel 4004 (‘71)Intel 8080Intel 8080Intel 8085Intel 8085Intel 80286Intel 80286Intel 80486Intel 80486Courtesy Intel© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesAutomating DesignAutomating DesignExploitation By AlgorithmsRegular StructuresLogic SynthesisRegularization of ConnectionFloorplanning (Localization of function)System Level Performance/Power/CostAllocation of Physical ResourcesCommunication/InterconnectHierarchy based on Sensitivity to LatencyWires to Link Protocols© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesA System-on-a-Chip: ExampleA System-on-a-Chip: ExampleCourtesy: Philips© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesDesign MethodologyDesign Methodology• Design process traverses iteratively between three abstractions: behavior, structure, and geometry• More and more automation for each of these steps© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesFloorplanningFloorplanningA Protocol Processor for Wireless© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesImplementation ChoicesImplementation ChoicesCustomStandard CellsCompiled CellsMacro CellsCell-basedPre-diffused(Gate Arrays)Pre-wired(FPGA's)Array-basedSemicustomDigital Circuit Implementation Approaches© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesImpact of Implementation ChoicesImpact of Implementation ChoicesEnergy Efficiency (in MOPS/mW)Flexibility(or application scope)0.1-11-1010-100100-1000NoneFullyflexibleSomewhatflexibleHardwired customConfigurable/ParameterizableDomain-specific processor(e.g. DSP)Embedded microprocessor© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesImplementation StrategiesImplementation StrategiesPLATechnology confined in cell macros (tiling)Cell based logicTechnology confined to cells (area)Both 1-d and 2-d solutionsTransistor Arrays (Gate arrays)Technology confined to layers (Below M1 fixed)© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesPLA: Programmable Logic ArrayPLA: Programmable Logic Arrayx0x1x2ANDplanex0x1x2Product termsORplanef0f1© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesTwo-Level LogicTwo-Level LogicInverting format (NOR-NOR) more effectiveEvery logic function can beexpressed in sum-of-productsformat (AND-OR)minterm© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesPLA Layout – Exploiting RegularityPLA Layout – Exploiting Regularityf0f1x0x0x1x1x2x2Pull-up devices Pull-up devicesVDDGNDAnd-PlaneOr-Plane© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesBreathing Some New Life in PLAsBreathing Some New Life in PLAsRiver PLAsA cascade of multiple-output PLAs.Adjacent PLAs are connected via river routing.P R E - C H A R G EPRE-CHARGEP R E - C H A R G EPRE-CHARGEB U F F E RB U F F E RBUFFERBUFFERP R E - C H A R G EPRE-CHARGEB U F F E RBUFFERP R E - C H A R G EPRE-CHARGEB U F F E RBUFFER•No placement and routing needed. •Output buffers and the input buffers of the next stage are shared.Courtesy B. Brayton© Digital Integrated Circuits2nd and F. Brewer 2003Design MethodologiesExperimental ResultsExperimental ResultsLayout of C2670Network of PLAs, 4 layers OTCRiver PLA,2 layers no additional routingStandard cell, 2 layers channel routingStandard cell,3 layers OTC0.20.611.40 2 4 6areadelayS C N P L A R P L AArea: RPLAs (2 layers) 1.23 SCs (3 layers) - 1.00, NPLAs (4 layers) 1.31 DelayRPLAs 1.04SCs 1.00 NPLAs 1.09 Synthesis time: for RPLA , synthesis time equals design time; SCs and NPLAs still need P&R.Also: RPLAs are regular and predictable© Digital Integrated Circuits2nd and F. Brewer 2003Design Methodologies2-d Cell Based: “Hard” Modules2-d Cell Based: “Hard” Modules25632 (or 8192 bit) SRAMGenerated by hard-macro module generator© Digital Integrated Circuits2nd and F. Brewer 2003Design Methodologies1-d Cell-based Design (standard cells)1-d Cell-based Design (standard cells)Routing channel requirements arereduced by presenceof more interconnectlayersFunctionalmodule(RAM,multiplier,)RoutingchannelLogic cellFeedthrough cellRows ofcells© Digital Integrated Circuits2nd and F. Brewer 2003Design