Impact of InterconnectInterconnect Impact on ChipNature of InterconnectINTERCONNECT CapacitanceCapacitance of Wire InterconnectCapacitance: The Parallel Plate ModelPermittivityFringing CapacitanceFringing versus Parallel PlateInterwire CapacitanceImpact of Interwire CapacitanceWiring Capacitances (0.5 mm CMOS)INTERCONNECT ResistanceWire ResistanceInterconnect ResistancePolycide Gate MOSFETSheet ResistanceExample: Intel 0.25 micron ProcessPowerPoint PresentationThe Lumped ModelThe Lumped RC-Model The Elmore DelayThe Ellmore Delay RC ChainWire ModelThe Distributed RC-lineStep-response of RC wire as a function of time and spaceRC-ModelsDriving an RC-lineDesign Rules of ThumbHomework 4© Digital Integrated Circuits2ndInverterImpact of InterconnectImpact of InterconnectInterconnectionFundamental limitation of Digital Technology at all scalesClasses of parasitics:–Capacitive–Resistive–Inductive (Impact usually package/board level)© Digital Integrated Circuits2ndInverterInterconnect Impact on ChipInterconnect Impact on Chip© Digital Integrated Circuits2ndInverter10 100 1,000 10,000 100,000Length (u)No of nets(Log Scale)Pentium Pro (R)Pentium(R) IIPentium (MMX)Pentium (R)Pentium (R) IINature of InterconnectNature of InterconnectLocal InterconnectGlobal InterconnectSLocal = STechnologySGlobal = SDieSource: Intel© Digital Integrated Circuits2ndInverterINTERCONNECTINTERCONNECTCapacitanceCapacitance© Digital Integrated Circuits2ndInverterCapacitance of Wire InterconnectCapacitance of Wire InterconnectVDDVDDVinVoutM1M2M3M4Cdb2Cdb1Cg d12CwCg4Cg3Vo ut2FanoutInterconnectVoutVinCLSimplifiedModel© Digital Integrated Circuits2ndInverterCapacitance: The Parallel Plate ModelCapacitance: The Parallel Plate ModelDielectricSubstrateLWHtdiElectrical-field linesCurrent flowWLtcdidiintLLCwireSSSSS1© Digital Integrated Circuits2ndInverterPermittivityPermittivity© Digital Integrated Circuits2ndInverterFringing CapacitanceFringing CapacitanceW - H/2H+(a)(b)© Digital Integrated Circuits2ndInverterFringing versus Parallel PlateFringing versus Parallel Plate(from [Bakoglu89])© Digital Integrated Circuits2ndInverterInterwire CapacitanceInterwire Capacitancefringing parallel© Digital Integrated Circuits2ndInverterImpact of Interwire CapacitanceImpact of Interwire Capacitance(from [Bakoglu89])© Digital Integrated Circuits2ndInverterWiring Capacitances (0.5 Wiring Capacitances (0.5 m CMOS)m CMOS)Layer N+ P+ Poly Poly2 M1 M2 M3Sub 420 730 87 -- 32 16 10aF/m2Ndif 2450aF/m2Pdif 2360aF/m2Poly 860 57 16 9aF/m2Poly2 52aF/m2M1 31 13aF/m2M2 32aF/m2Sub(fr) 310 250 76 59 39aF/mPoly(fr) 61 38 28aF/mM1(fr) 51 33aF/mM2(fr) 52aF/m© Digital Integrated Circuits2ndInverterINTERCONNECTINTERCONNECTResistanceResistance© Digital Integrated Circuits2ndInverterWire Resistance Wire Resistance WLHR = H WLSheet ResistanceRoR1R2© Digital Integrated Circuits2ndInverterInterconnect Resistance Interconnect Resistance© Digital Integrated Circuits2ndInverterPolycide Gate MOSFETPolycide Gate MOSFETn+n+SiO2PolySiliconSilicidepSilicides: WSi2, TiSi2, PtSi2 and TaSiConductivity: 8-10 times better than Poly© Digital Integrated Circuits2ndInverterSheet ResistanceSheet Resistance© Digital Integrated Circuits2ndInverterExample: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric© Digital Integrated Circuits2ndInverterInterconnectInterconnectModelingModeling© Digital Integrated Circuits2ndInverterThe Lumped ModelThe Lumped ModelVoutDrivercwi reVinCl u m p e dRd r iv e rVo u t© Digital Integrated Circuits2ndInverterThe Lumped RC-ModelThe Lumped RC-ModelThe Elmore DelayThe Elmore Delay© Digital Integrated Circuits2ndInverterThe Ellmore DelayThe Ellmore DelayRC ChainRC Chain© Digital Integrated Circuits2ndInverterWire ModelWire ModelAssume: Wire modeled by N equal-length segments For large values of N:© Digital Integrated Circuits2ndInverterThe Distributed RC-lineThe Distributed RC-line© Digital Integrated Circuits2ndInverterStep-response of RC wire as a Step-response of RC wire as a function of time and spacefunction of time and space0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 500.511.522.5time (nsec)voltage (V)x= L/10 x = L/4 x = L/2 x= L© Digital Integrated Circuits2ndInverterRC-ModelsRC-Models© Digital Integrated Circuits2ndInverterDriving an RC-lineDriving an RC-lineVi nRsVo u t(rw,cw,L)© Digital Integrated Circuits2ndInverterDesign Rules of ThumbDesign Rules of Thumbrc delays should only be considered when tpRC >> tpgate of the driving gateLcrit >>  tpgate/0.38rcrc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the linetrise < RCwhen not met, the change in the signal is slower than the propagation delay of the wire© MJIrwin, PSU, 2000© Digital Integrated Circuits2ndInverterHomework 4Homework 41. For the AMIS 0.5um technology, create an equivalent RC/Elmore SUE model using the Mosis parametric test results (amis05.txt from web site). This model should include the effective gate capacitance, source and drain parasitic junction capacitances and equivalent resistance for NMOS and PMOS, L=0.5um as a function of W in um. Use this model to estimate the sizes of the transistors in the ring oscillator test for the standard and wide case from the given performance data. (Do this carefully, this is a useful model!!)2. Rabaey Chap. 4 on-line problems: 1, 4, 7,