Putting it all together— Chip Level IssuesFull Chip IssuesChip Power RequirementsPower Coupled NoiseNoise to Jitter Conversion: FundamentalsGate Behavior with NoiseLogic Current ProfilePower DistributionPower and Ground DistributionPower Distribution MeshIR DropPower Rail IR DropResistance and the Power Distribution Problem3 Metal Layer Approach (EV4)4 Metal Layers Approach (EV5)6 Metal Layer Approach – EV6Bypass Calculation IParasitic BypassElectromigration (1)Electromigration (2)Metal MigrationClockingClock DistributionMore realistic H-treeThe Grid SystemExample: DEC Alpha 2116421164 ClockingPowerPoint PresentationClock Skew in Alpha ProcessorSlide 3021264 ClockingEV6 Clock ResultsEV7 Clock HierarchyCapacitive Coupling (Coupling Cross Talk)Capacitive Cross Talk Driven NodeDealing with Capacitive Cross TalkShieldingInductive Issues in ClockingPackaging and Board InterfacePackaging RequirementsBonding TechniquesTape-Automated Bonding (TAB)Flip-Chip BondingCu Flip-Chip TechnologyPackage-to-Board InterconnectPackage TypesPackage ParametersMulti-Chip ModulesPackage ParasiticsPower System ModelImperfect Bypass CapacitorsChip Bypass CapacitorsPower Supply InductanceBypass Reprise: LC step responseBasic Bypass RulesDe-coupling Capacitor RatiosEV6 De-coupling CapacitancePCB SignalingThe Transmission LineDesign Rules of ThumbMatched TerminationParallel Termination─ Transistors as ResistorsOutput Driver with Varying TerminationsL di/dtL di/dt: SimulationSimultaneous Switching NoiseDealing with Ldi/dtEV6 WACCPadsPads-- Chip to Board InterfaceChip PackagingPad FramePad ExampleBus DetailSeal RingSlide 76Chip to Board Interface -- Pad DesignDriving Large CapacitancesUsing Cascaded BuffersOutput Driver DesignDelay as a Function of F and NSlide 82How to Design Large TransistorsBonding Pad DesignESD ProtectionSlide 86© Digital Integrated Circuits2nd and F. BrewerInterconnectPutting it all togetherPutting it all together——Chip Level IssuesChip Level Issues© Digital Integrated Circuits2nd and F. BrewerInterconnectFull Chip IssuesFull Chip IssuesNoisePower DistributionClockingPackagingPads© Digital Integrated Circuits2nd and F. BrewerInterconnectChip Power RequirementsChip Power RequirementsLarge Scale Chip Power PhenomenalPentium 4 @ 0.13um has 85A Peak Package Current@ 1.5V requires .15/85 = 1.8m total power network resistanceOn-chip peak current risetime is <100pS!IDD changes on many time scales (DC to GHz)clock gatingTimeAverageMaxMinPower© Digital Integrated Circuits2nd and F. BrewerInterconnectPower Coupled NoisePower Coupled NoiseDroop due to IR drop, LdI/dt noise and Supply InductanceModulates behavior of GatesSignalling FailureReduction of Noise Budget (Can you afford dynamic logic)Reduction of System PerformanceIncrease in Power DissipationReduction of device reliability–Hot Electrons–Oxide Damage–Electromigration© Digital Integrated Circuits2nd and F. BrewerInterconnectNoise to Jitter Conversion: Noise to Jitter Conversion: FundamentalsFundamentals•Uncertainty of threshold reference (A from power supply noise) determines jitter–The buffer can switch (threshold) anywhere in this region (A’)–The slower the rise time the more opportunity is presented to PWR noise•Amount of jitter directly proportional to the magnitude of the noise/ripple/GND bounce– B (jitter) = A (noise) * dt/dV Internal PWR or GND RailCore CLK at BUFG InputBAA’© Digital Integrated Circuits2nd and F. BrewerInterconnectGate Behavior with NoiseGate Behavior with NoiseEffective propagation time can be longer or shorter due to noiseDelay is proportional to noise magnitudeNoise induced delay can be either positive or negativeVdd1Vdd2Gnd2Gnd1tGnd2Gnd1Vdd2Vdd1© Digital Integrated Circuits2nd and F. BrewerInterconnectLogic Current ProfileLogic Current ProfileAssume triangle current profile: Peak CurrentAverage Current K denotes the probability of switching K=.5 for a clock K=.2 for a heavily used part of microprocessorK=.1 or less for typical asicddLoadVCQ rddLoadrpeaktVCtQi1.18.12clkddLoadavgtVkCi © Digital Integrated Circuits2nd and F. BrewerInterconnectPower DistributionPower DistributionLow-level distribution is in Metal 1Higher ResistancePower has to be ‘strapped’ in higher layers of metal.The spacing is set by IR drop, electromigration, inductive effectsAlways use multiple contacts on straps© Digital Integrated Circuits2nd and F. BrewerInterconnectPower and Ground DistributionPower and Ground DistributionGNDVDDLogicGNDVDDLogicGNDVDD(a) Finger-shaped network (b) Network with multiple supply pins© Digital Integrated Circuits2nd and F. BrewerInterconnectPower Distribution MeshPower Distribution MeshVDDVDDBC:Connection point,Current contributionCurrent flowing path:VDD pinModule A(1)(2)(3)(5)(6)© Digital Integrated Circuits2nd and F. BrewerInterconnectIR DropIR DropIR drop is proportional to local peak currentPeak current reduced by parasitic bypass capacitanceGeometry to estimate RdistInductance usually ignored since small compared to IR–Capacitive coupling is very large, inductance is the inverse–Not true for low resistance busses (e.g. pad frame wiring)Local peak strongly affected by synchronization of clocking–Intentional skew (DAC ’98 Vittal)ondistributipeakdropRIV dtdILRIViiipathidrop© Digital Integrated Circuits2nd and F. BrewerInterconnectPower Rail IR DropPower Rail IR DropDistributed model of current loads and resistanceSupply from both sides, assume uniform loadSupply from one side, uniform: 4x as large = IR/28(max)totaltotaldropRIV © Digital Integrated Circuits2nd and F. BrewerInterconnectResistance and the Power Resistance and the Power Distribution ProblemDistribution ProblemSource: Cadence• Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction• Heavily influenced by packaging technologyHeavily influenced by packaging technologyBeforeBeforeAfterAfter© Digital Integrated Circuits2nd and F. BrewerInterconnect3 Metal Layer Approach (EV4)3 Metal Layer Approach (EV4)3rd “coarse and thick” metal layer added to thetechnology for EV4 designPower supplied from two sides of the die via 3rd metal layer2nd metal layer used to form power grid90% of 3rd metal layer used for power/clock routingMetal 3Metal 2Metal 1Courtesy Compaq© Digital Integrated Circuits2nd