1BR 1/00 1Implementation Technologies• We can implement a design with many different implementation technologies - different implementation technologies offer different tradeoffs– VHDL Synthesis offers an easy way to target a model towards different implementations– There are also retargeting tools which will convert a netlistfrom one technology to another (from a standard cell implementation to a Field Programmable Gate Array implementation).BR 1/00 2Available implementation technologies• Full Custom• Standard Cell• Gate Array• Field Programmable Gate Arrays (FPGAs)• Complex PLDs (CPLDs)• Programmable Logic Devices (PLDs)BR 1/00 3Full Custom• Designer hand draws geometries which specify transistors and other devices for an integrated circuit. Designer must be an expert in VLSI (Very Large Scale Integration) design.• Can achieve very high transistor density (transistors per square micron); unfortunately, design time can be very long (multiple months).• Involves the creation of a a completely new chip, which consists of about a dozen masks (for the photolithographic manufacturing process). Mask creation is the expensive part.BR 1/00 4Full Custom (cont)• Offers the chance for optimum performance. Performance is based on available process technology, designer skill, and CAD tool assistance.• Fabrication costs are high - all custom masks must be made so non-recurring engineering costs (NRE) is high (in the thousands of dollars). If required number of chips is high then can spread these NRE costs across the chips.• The first custom chip costs you about $200,000, but each additional one is much cheaper.BR 1/00 5Full Custom (cont)• Fabrication time from geometry submission to returned chips is at least 6-8 weeks.• Full custom is currently the only option for mixed Analog/Digital chips.• An example VLSI layout is shown below.BR 1/00 6Standard Cell• Designer uses a library of standard cells; an automatic place and route tool does the layout. Designer does not have to be a VLSI expert.• Transistor density and performance degradation depends on type of design being done. Not bad for random logic, can be significant for datapath type designs.– Quality of available library and tools make a signficantdifference.• Design time can be much faster than full custom because layout is automatically generated.2BR 1/00 7Standard Cell (cont)• Still involves creation of custom chip so all masks must still be made; manufacturing costs same as full custom.• Fabrication time same as full custom.BR 1/00 8Gate Array• Designer uses a library of standard cells. The design is mapped onto an array of transistors which is already created on a wafer; wafers with transistor arrays can be created ahead of time. A routing tool creates the masks for the routing layers and "customizes" the pre-created gate array for the user's design.• Transistor density can be almost as good as standard cell. Design time advantages are the same as for standard cell.• Performance can be very good; again, depends on quality of available library and routing tools.BR 1/00 9Gate Array (cont)• Fabrication costs are cheaper than standard cell or full custom because the gate array wafers are mass produced; the non recurring engineering csts are lower because only a few (1-3) unique routing masks have to be created for each design.• Fabrication time can be extremely short (1-2 weeks) because the wafers are already created and are only missing the routing layers. The more routing layers, the higher the cost, the longer the fabrication time, but the better usage of the available transistors on the gate array.• Almost all high volume production of complex digital designs are done in either Standard Cell or Gate Array– Gate arrays used to be more popular, but recently Standard cells has shown a resurgence in use.BR 1/00 10Programmable Logic• Logic devices which can be programmed/configured on the desktop.• Three families (in increasing density)– PALS (Programmable Array Logic), Programmable Logic Devices– Complex PLDs– Field Programmable Gate Arrays• It should be noted that memories are the earliest type of programmable logicBR 1/00 11PALs (Programmable Array Logic)• An early type of programmable logic - still in common use today.• Logic is represented in SOP form (Sum of Products)• The number of PRODUCTs in an SOP form will be limited to a fixed number (usually 4-10 Product terms).• The number of VARIABLEs in each product term limited by number of input pins on PLD (usually a LOT, minimum of 10 inputs• The number of independent functions limited by number of OUTPUT pins. BR 1/00 1222V10 PLD3BR 1/00 13Complex PLDs• What is the next step in the evolution of programmable logic?–More gates!• How do we get more gates? We could put several PALs on one chip and put an interconnection matrix between them!!– This is called a Complex PLD (CPLD).BR 1/00 14Cypress CPLDEach logic block is similar to a 22V10.Programmable interconnect matrix.BR 1/00 15Any other approaches?Another approach to building a “better” PLD is place a lot of primitive gates on a die, and then place programmable interconnect between them:BR 1/00 16Field Programmable Gate ArraysThe FPGA approach to arrange primitive logic elements (logic cells) arrange in rows/columns with programmable routing between them.What constitutes a primitive logic element? Lots of different choices can be made! Primitive element must be classified as a “complete logic family”.• A primitive gate like a NAND gate • A 2/1 mux (this happens to be a complete logic family)• A Lookup table (I.e, 16x1 lookup table can implement any 4 input logic function).Often combine one of the above with a DFF to form the primitive logic element. BR 1/00 17Other FPGA features• Besides primitive logic elements and programmable routing, some FPGA families add other features • Embedded memory– Many hardware applications need memory for data storage. Many FPGAs include blocks of RAM for this purpose• Dedicated logic for carry generation, or other arithmetic functions• Phase locked loops for clock synchronization, division, multiplication.BR 1/00 18Other FPGA Comments• Performance is usually several factors to an order of magnitude lower than standard cell. Performance depends heavily on quality of FPGA technology.• Design time advantages are the same as for standard cell (use same type of cell/macro