Slide Number 1VHDLA Brief History of VHDLVHDL vs. VerilogExamplesLabeling and FormattingCommentsDesign EntityEntity DeclarationArchitectureEntity Declaration and ArchitecturePort ModesLibrary declarationsFundamental parts of a libraryLibrariesSTD_LOGIC typeSignalsStandard Logic VectorsVectors and ConcatenationVHDL Design StylesSlide Number 21Dataflow Description Example: Structural ArchitectureStructural DescriptionExample: Behavioral ArchitectureBehavioral DescriptionSlide Number 27Majority Gate with Temporary SignalsMajority Gate with when-else statementConcurrent Versus Sequential StatementsMajority Gate using process blockComments on process block modelUse of if-elseUnassigned outputs in Process blocksComments on ‘bad’ ArchitectureSlide Number 36Comments on Priority ExamplePriority Circuit with just IF statements.Priority Circuit with when-else statements.4-to-1 mux with 8 bit DatapathsComments on Mux example4-to-1 Mux using Case Sequential StatementLogical Shift Left by 14 Bit Ripple Carry Adder4 Bit Adder using For StatementComments on for-loop statementDepartment of Electrical and Computer EngineeringMississippi State UniversitySherif Abdelwahed Introduction to VHDLComputer Aided Digital Systems Design - EE 4743/6743VHDL VHDL is a language for describing digital hardware used by industry worldwide¾ VHSIC (Very High Speed Integrated Circuit) Hardware Description Language  A VHDL description of a digital system can be transformed into a gate level implementation. This process is known as synthesis. VHDL is the product of a US Government request for a new means of describing digital hardware.  The VHSIC Program was an initiative of the Defense Department to push the state of the art in VLSI technology, and VHDL was proposed as a versatile hardware description language.A Brief History of VHDL June 1981: Woods Hole Workshop July 1983: contract awarded to develop VHDL¾ Intermetrics¾ IBM¾ Texas Instruments August 1985: VHDL Version 7.2 released December 1987: VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standardVHDL vs. VerilogVHDL VerilogGovernment Developed Commercially DevelopedAda based C basedStrongly Type Cast Mildly Type CastDifficult to learn Easier to LearnMore Powerful Less PowerfulExamples VHDL Example:process (clk, rstn) beginif (rstn = '0') thenq <= '0';elseif (clk'event and clk = '1') thenq <= a + b;end if;end process; Verilog Example:always@(posedge clk or negedge rstn)beginif (! rstn)q <= 1'b0;elseq <= a + b;endLabeling and Formatting VHDL is not case sensitive¾ databus, DataBus, DATABUS are all equivalent VHDL is a free format language. No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way.¾ Example:if (a=b) thenorif (a=b) then orif (a =b) thenare all equivalentComments Comments in VHDL are indicated with a double dash “‐‐”¾ Comment indicator can be placed anywhere in the line¾ Any text that follows in the same line is treated as a comment¾ Carriage return terminates a comment¾ No method for commenting a block extending over a couple of lines¾ Examples:‐‐ main subcircuitData_in <= Data_bus; ‐‐ reading data from the input FIFO Explain function of module to other designers Explanatory, not just restatement of code Locate close to code described¾ Put near executable code, not just in a headerDesign Entityentity declarationarchitecture 1architecture 2architecture 3design entity Every VHDL model is composed of an entity and at least one architecture. Entity describes the interface to the model (inputs, outputs) Architecture describes the behavior of the model Can have multiple architectures for one entity (we will only use one in this class).ENTITY nand_gate ISPORT(a : IN STD_LOGIC;b : IN STD_LOGIC;z: OUT STD_LOGIC);END nand_gate;Entity Declaration Entity Declaration describes the interface of the component, i.e. input and output ports.Reserved wordsEntity namePort namesPort typeSemicolonNo SemicolonPort modes (data flow directions)Architecture Describes an implementation of a design entity.  Architecture example:ARCHITECTURE model OF nand_gate ISBEGINz <= a NAND b;END model; Entity nameArchitecture nameArchitecture codeEntity Declaration and ArchitectureLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY nand_gate ISPORT(a : IN STD_LOGIC;b : IN STD_LOGIC;z: OUT STD_LOGIC);END nand_gate;ARCHITECTURE model OF nand_gate ISBEGINz <= a NAND b;END model;nand_gate.vhdPort ModesThe Port Mode of the interface describes the direction in which data travels with respect to the component¾ In: Data comes in this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment.¾ Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment. ¾ Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment. ¾ Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operatorLibrary declarationsLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY nand_gate ISPORT(a : IN STD_LOGIC;b : IN STD_LOGIC;z: OUT STD_LOGIC);END nand_gate;ARCHITECTURE model OF nand_gate ISBEGINz <= a NAND b;END model;Library namePackage namePackage partFundamental parts of a libraryLIBRARYPACKAGE 1 PACKAGE 2TYPESCONSTANTSFUNCTIONSPROCEDURESCOMPONENTSTYPESCONSTANTSFUNCTIONSPROCEDURESCOMPONENTSLibraries ieee std workNeed to be explicitlydeclaredVisible by defaultSpecifies multi-level logic system,including STD_LOGIC, and STD_LOGIC_VECTOR data typesSpecifies pre-defined data types(BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc.Current designs after compilationSTD_LOGIC typeValue Meaning‘X’ Forcing (Strong driven) Unknown‘0’Forcing (Strong driven) 0‘1’Forcing (Strong driven) 1‘Z’High Impedance‘W’Weak (Weakly driven) Unknown‘L’Weak (Weakly driven) 0.Models a pull down.‘H’Weak (Weakly driven) 1. Models a pull up.‘-’ Don't CareSignalsSIGNAL a : STD_LOGIC;SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);wireabusb18Standard