Slide Number 1Slide Number 2Slide Number 3Slide Number 4Course OutlineSlide Number 6Course WebsiteSlide Number 8Slide Number 9Slide Number 10Slide Number 11Slide Number 12Slide Number 13Slide Number 14Slide Number 15Slide Number 16Department of Electrical and Computer EngineeringMississippi State UniversitySherif Abdelwahed IntroductionComputer Aided Digital Systems Design - EE 4743/6743Introduction and ContactsVery Short Bio  Ph.D., University of Toronto, Canada, 2002 Thesis: Interacting DES, modeling, verification and supervisory cont. 2000-2001: Research Scientist, Rockwell Science Center, CA 2002-2007: Research Assistant Professor, Vanderbilt University, TN 2007-present: Assistant Professor, ECE Department, MSUContact Information  Office: Simrall 333 Phone: 325-6903 Email: [email protected] WWW: www.ece.msstate.edu/~sherif Office Hours: MW 1:30-3:00 pm, or by appointmentLectures and Labs Class meeting MW 10:00-10:50am, Simrall 102¾ Will have lectures on Fridays also for the first 3-5 weeks to get a fast start on materials¾ Fridays will be mostly used for tests  Greater class load in the beginning to prepare for lab. More time for labs and project at end of semesterLabs Lab session attendance is required to hear TA explanation of lab assignment. Lab at Simrall workstation lab, 1st floor (Simrall 132).  Lab assignments due ONE WEEK from your assigned lab time unless otherwise notedRequirements and ResourcesPrerequisite Topics Binary, Octal, and Hexadecimal numbering systems Boolean Algebra, Gate level minimization Combinational and sequential building blocks. Memory devices Synchronous sequential networks (finite state machinesResources Class slides – main source for tests Books:  R. Reese, Introduction to Logic Synthesis using Verilog HDL, 2006  M. D. Ciletti, Advanced Digital Design With the Verilog HDL, (Optional). Diligent Basys development board Xilinx WebPack software and documentation (Downloadable)Course Outline Verilog HDL: types of Verilog (Structural, Behavioral),  Finite State Machines: ASM, Verilog implementations, FSM timing Datapath design: FMS controller design, memory types and design issues, asynchronous vs. synchronous control Timing analysis: computing different delays across the circuit, techniques to increase the clock rate Scheduling: design constraints, date flow graph, datapath design, clock and register scheduling, techniques to increase initiation rate Pipelining: Requirement analysis, design issues and implementation approach IO Technologies: signaling types (applications, technologies, advantages, and disadvantages), eye diagram. Implementations technologies: ROMs, PLDs, FPGAs, Gate Arrays, Standard cells, Custom logic. Design for Test techniques: Fault analysisCourse ObjectivesBy the end of the course, you should learn: Combinational, Sequential, and Structural Verilog HDL. Write a textual description of a digital schematic which can be compiled and downloaded into a configurable chip. Implementation Technologies. Identify target implementations given design guidelines and constraints.  Datapath Design and Control. Given a datapath, select and design a control mechanism (FSM, Microcode).  System Timing. Determine worst-case scenarios for timing delays given a specific design.  Testing and Evaluation. Create a test program to check for opens and shorts in a given design.Course Website Current website¾ www.ece.msstate.edu/wiki/index.php/ECE4743_Digital_Systems_Design Resource¾ Syllabus¾ Course updates¾ Tutorials¾ Lecture notes, supplemental readings¾ Previous homework assignments ¾ Project information¾ Sample tests and homework Check it oftenCourse Software  We will be using a package called Xilinx ISE WebPack for digital logic programming. Can be downloaded from the Xilinx webpage  Software is the same as used by practicing engineers in industry We will discuss how to install and use the software in lab.  The labs will be oriented around your laptops, so you will need to install the software yourself.  You must have the software downloaded before coming to lab since it is a very large download (~850MB). Instructions for downloading it are included in lab 1.  This software is also available on the workstations in the lab if you do not have a laptop.Course Hardware  Purchase development board¾ Digilent Basys board, ¾ Can be purchased directly from Digilent Inc. homepage ($59). Each board has 8 LEDs, 8 switches, 4 push buttons, and a 4 digit numerical display.  There are also connections for a VGA monitor and a PS/2 port for keyboards/mice. Reference manual and board schematic are available to download Strongly recommending doing the labs on your laptops  If you don't have a suitable laptop, some computers will be available in lab for development and programmingClass Projects Team project this semester lasting 3-4 weeks Uses the Basys development board interfaced with inputs and output devices Potential project topics will be posted later During the semester you will submit a proposal for your project¾ Must be approved by the instructor¾ The project must have a high relevance factor and be attractive Several milestones¾ Forming teams¾ Project status reports¾ Project demonstrations¾ Project final report More details coming later in the courseAttendance  Not taking attendance for classes¾ Expected for tests and finals¾ NO make-up tests¾ possible exceptions for extreme cases Tests based on in-class discussion STRONGLY RECOMMEND coming to class Ask QUESTIONS during CLASS to SLOW things downGrading and Tests Grad distribution Tests (5): 40% Final: 30% Lab: 20% Project: 10%Tests You must achieve at least a 60% grade average on ALL in-class material (exams+ lab+ project) to pass the course. There will be five tests (in addition to the final and lab test). Your lowest test grade will be dropped Previous tests are posted on the course website. Test dates will be announced at class least one week in advanceTest Re-grade policy You may request one re-grade for each exam ¾ In writing justify the change¾ Even for small errors Submit your exam and your statement¾ To me personally, or under my door, or in my mailbox¾ However, I cannot guarantee that I will receive the submission unless it is given to me