Slide Number 1Composition of Digital SystemsDatapathsControllerData TransferTri-State BusesModeling Three-State RegistersModeling Tristate BusSlide Number 9Design Case StudyNormal RAM InterfaceDatapath Components Needed How do we put it together?Datapath Block DiagramSlide Number 15FSM InterfaceWhat operations do we need for FSM?Controller ASM Datapath and ControlCommentsDesign ImplementationDesign ImplementationDesign ImplementationTips and TricksSynchronous vs. Asynchronous RAMUsing Counters to Drive AddressMemory Design IssueMemory Design IssueMemory Design IssueSynchronous RAMSynchronous RAM Asynchronous RAM TimingSynchronous RAM TimingSynchronous RAM TimingAsynchronous vs. Synchronous ControlDepartment of Electrical and Compute EngineeringMississippi State UniversitySherif Abdelwahed Datapath DesignComputer Aided Digital Systems Design - EE 4743/6743Composition of Digital Systems Most digital systems can be partitioned into two types of modules:¾ Datapath: perform data-processing operations between registers¾ Controller: determine the sequence of those operationsDatapaths The datapath is the portion of the circuit that contains components that transform input data signals into output data signals.  Datapaths may be purely combinational or they may also contain synchronous components such as dedicated counters. A typical datapath often consists of several components:¾ Registers¾ Memory units (LUT)¾ Arithmetic/logic units (ALU)¾ Comparators¾ Multiplexers ¾ Tristate busesController Controller can be programmable or non-programmable Programmable¾ Has a program counter which point to next instruction¾ Instructions are held in a RAM or ROM externally¾ Microprocessor is an example of programmable controller Non-Programmable¾ Once designed, implements the same functionality¾ Another term is a “hardwired state machine” or “hardwired instructions”¾ We will be focusing primarily on the non-programmable type in this courseData TransferMultiplexer-based Transfer Used when a register receives data from two or more different sources at different timesBus-based Transfer Can have only one source but multiple destinations at a timeTri-State Buses A bus can be constructed using three-state buffers Several three-state buffer outputs can be connected together¾ Avoid the high fan-in OR in multiplexers¾ Delay time and logic complexity can be reduced The signals can travel in two directions on a three-state bus¾ EN=1: output, EN=0: input¾ Simplify the interconnectionsModeling Three-State Registers To declare a bidirectional data port, inout type is used instead of input or outputmodule TriReg(CLK, Rst, EN, Load, Data);input CLK, Rst, EN, Load;inout Data;reg int_data, Data;always @(posedge CLK) beginif (Rst) int_data = 0;else if (Load) int_data = Data;endalways @(int_data or EN) beginif (EN) Data = int_data;else Data = 1`bz;endendmoduleModeling Tristate Bus To model the behavior of a three-state bus, tri type is used instead of wire¾ tri: has the same properties of wire but indicates more than one drivers may connect to itmodule TriBus(CLK, Rst, E2, E1, E0, L2, L1, L0);input CLK, Rst, E2, E1, E0, L2, L1, L0;tri databus;TriReg R0(CLK, Rst, E0, L0, databus);TriReg R1(CLK, Rst, E1, L1, databus);TriReg R2(CLK, Rst, E2, L2, databus);EndmoduleDesign Process Layout in plain English what you want to accomplish Design your datapath Design your FSM controller (ASM chart) Implement your datapath Implement your FSM Debug  ReviseDesign Case Study Create a synchronous RAM block that has a block transfer capability Preserve normal RAM operation When ‘xfer’ input asserted, ¾ assert BUSY output ¾ transfer “WCNT” # of words¾ Copy from address “FROM”¾ Write into address “TO” Values of WCNT, FROM, TO are loaded before transfer operation started RAM size: 64 x 80000000011111111WCNTFROMTONormal RAM Interface Inputs¾ clk¾ we - write enable for RAM¾ DIN[7..0] Data bus to RAM¾ Addr[5..0] Address bus to RAM.  Outputs¾ DOUT[7..0]Datapath Components Needed  Need the RAM  Counters for values¾ Word Count¾ To¾ From MuxesHow do we put it together? Start with how the RAM is typically set up We know we’ll need to direct the addresses stored in FROM, TO registers to the RAM’s address We know we’ll need to copy data from the RAM back into the RAM We know that we need to increment the addresses in both blocks until WCNT is reachedDatapath Block DiagramTO CntrFROM CntraddrdoutdataAddr [5..0]Din[7:0]Dout [7:0]Control lines not shown on datapath diagramWCNT CntrSync RAMWhat Control Lines do we need from FSM? Counters: Load lines for WCNT, TO, FROM registers driven externally and not under FSM control.  Count enables for these counters need to be exercised by FSM.  WCTN will be configured to count DOWN, the TO,FROM counters will count UP. Mux Selects: When doing transfer operation, counters will be driving RAM address lines and RAM input data line will be a feedback from the RAM output.  RAM: The WE of the RAM needs to be an OR of the external WE and a WE that is provided by the FSM.FSM Interface Inputs:¾ Clk, Reset¾ xfer – kicks off transfer operation ¾ cnt_words[5:0] – WCNT counter value (need to check this to see if finished) Outputs:¾ busy – busy output¾ addr_sel[1:0] – mux select line for addr muxes¾ ce_from, ce_to, ce_words – count enables for FROM, TO, WCNT counters¾ fsm_we – WE to RAM¾ data_sel – mux select line for RAM input data muxWhat operations do we need for FSM? Wait for transfer command (FSM simply waits for ‘xfer’ input to be asserted). Read a value from RAM using FROM counter address; increment the FROM counter and decrement the WCNT counter  Write data value to RAM via TO address counter; increment the TO counter. Loop to read state unless WCNT counter value = 0.Three DISTINCT operations, need three STATES in FSM. Cannot do both a Read and Write in the same clock cycle.Controller ASM addr_sel = CPU_ADDRData_sel= CPU_DATAxfer?busy, ce_from, ce_wordsdata_sel= RAM_OUTPUTaddr_sel = FROM_CNTRbusy, ce_to, fsm_we data_sel = RAM_OUTPUTaddr_sel = TO_CNTcnt_words = 0?YesNoNoYesS0S1S2Datapath and ControladdrdoutDataweAddr[5..0]Din[7:0]Dout[7:0]decodeDin[1:0]cmd_weTO CntrldendinFROM CntrldendinWCNT Cntrldendinwefsm_wedata_seladdr_selce_toce_fromce_wordsxferFSMcnt_wordsSync RAMComments It only works