Creating a GDS File for MOSIS Chip Fabrication The layout information of schematics that we create in Cadence Virtuoso layout Editor is available as a gds file which can be sent to MOSIS for fabrication purposes To create a gds file of your layout go through the following process Go to cadence directory and create 2 folders gdsfiles and mapfile using the mkdir command cadence6720 mkdir gds files Now to begin the generation of the gds file go to the command interpreter window CIW and hit file export stream 1 The stream out window comes up Fill in the details as follows These may vary according to your directory cell and library names Run Directory Library Name Top Cell Name View Name Output Output File cadence6720 gds files your library name inverter layout Stream DB inverter gds Leave other fields unchanged Make sure that Error Message Filed contains PIPO log or any other file name you like Don t close the window 2 Click on the user defined data Stream out User Defined Data window comes up Fill in Layer Map Table field as home cs5710 cadence map files stream4gds map Make sure that Convert Pin to selection is geometry Leave other fields unchanged Click OK 3 Back in the Virtuoso R Stream Out window Click OK This starts the stream out process PIPO STRMOUT is running PID ipc appears in the icfb ciw If you did something wrong in the previous steps you will get an error message Go back and make necessary corrections based on the error message and restart the stream out process The stream out process takes a few minutes When done STRMOUT Popup Message window comes up Click OK 4 Check your gdsfiles directory to see of the required gds file is created 5 The warnings if any will be in PIPO LOG Depending on what you put in your layout you might have warnings about text and other annotation layers not being translated This is fine since they are non electrical layers 6 To have your chip fabricated in this class you will need to provide the following information A complete GDS file of your chip A checksum and byte count number for your final GDS file You will need to use the mosiscrc exe checksum program available at https www mosis org Webforms fabricate doc html checksum type The cell name of the complete chip layout The number of pads on your chip including pads not connected to anything but present in the layout This is usually 40 The X and Y size of your layout in microns This is usually 1500 1500 Email address es of designers A short name for your chip A one sentence description of your chip