EE CS 5720 6720 Layout Assignment 1 Basic Subcircuits In this assignment you will draw composite layout for simple analog CMOS subcircuits and use LVS Layout Vs Schematic to verify that your layout matches a drawn schematic For each of the five problems listed below turn in the following A printout of the circuit schematic that you drew in the Cadence Virtuoso schematic editor A printout of the layout Zoom in so your layout occupies the entire screen A printout of the LVS output file showing that the layout exactly matches the schematic 1 Draw the schematic and layout for the simple nMOS current mirror shown below in out VSS For both transistors make W 15 0 m and L 1 8 m Label the input and output as in and out respectively and use metal1 first layer metal for these signals Label VSS as VSS and connect this node to metal2 secondlayer metal You must first connect the nFET sources to metal1 as you did in the layout tutorial only metal1 can contact directly to active or poly but you should now use a via to connect metal1 to a strip of metal2 It is common practice to distribute commonlyused voltages like VSS VDD or biases across a chip on higher level metal layers Remember metal2 is above metal1 and the two layers are separated by an insulating layer so you can cross metal1 and metal2 wires Include at least one substrate contact tied to VSS It is good layout practice to include a substrate contact near every 4 8 nMOS transistors A suggested not required layout for the current mirror is shown below but not all layers are shown and the transistors are not drawn to scale in terms of W L ratio Active Polysilicon Contact Metal in out ground 2 Draw the schematic and layout for the pMOS source follower shown below VDD out bias in VSS For both mirror transistors make W 15 0 m and L 1 8 m Make the source follower transistor have W 30 0 m and L 1 2 m Label bias in and out on metal1 Label VDD on metal2 Label VSS on metal3 the third layer metal layer the top metal layer in this process You will have to use a via to connect metal1 to metal2 then use a via2 to connect metal2 to metal3 The mirror transistors should share a single well which should be tied to VDD with a well contact The source follower transistor will need its own isolated well that will be tied to its source Make sure to observe the appropriate well to well spacing DRC rule 3 Draw the schematic and layout for the pMOS differential pair shown below VDD in1 bias in2 out1 out2 For both mirror transistors make W 15 0 m and L 1 8 m Make the differential pair transistors have W 60 0 m and L 0 6 m Label bias in1 in2 out1 and out2 on metal1 Label VDD on metal2 All the transistors have their wells connected to VDD so they can all share one well 4 Repeat problem 3 but now draw each of the differential pair transistors as four parallel transistors each having W 15 0 m and L 0 6 m Refer to Figure 2 17 in Johns Martin for the most efficient way to draw the layout You will need to alter your schematic in order for this to LVS correctly Create a multiplicity of four transistors for each differential pair transistor You don t have to draw additional transistors just set W 15 0 m and M 4 in the transistor properties in the schematic editor This multi fingered gate layout is a standard technique used to draw transistors with large W L values Not only does it result in compact layout it also reduces the series resistance that can be a problem in long polysilicon gates 5 Draw the schematic and layout for the RC circuit shown below R1 in out C1 Label GND in and out on metal1 Use high resistance poly2 electrode for the resistor and poly poly2 poly electrode for the capacitor Since the lower poly layer has significant parasitic capacitance to the substrate tie this layer to ground and tie the poly2 electrode layer to out Note Cadence labels the poly2 layer electrode since it is used as a plate on capacitors Make R1 approximately 100k and C1 approximately 1 pF The minimum width of poly2 electrode is 5 1 5 m but make your resistor have a width of 10 3 0 m to improve matching characteristics If you wish you can snake the resistor as shown in Figure 2 23 to make the layout more compact For this problem report the extracted values of R1 and C1 Write this on your layout printout next to the resistor and capacitor layout The extracted values should be within 2 of the values requested above