ECE CS 5720 6720 Layout Assignment 2 Op Amp Layout In this assignment you will draw composite layout for a CMOS op amp with bias generator and use LVS Layout Vs Schematic to verify that your layout matches a drawn schematic Enter the schematic of the op amp and bias generator shown below VDD Q5 Q12 Q11 Q6 Q8 vOUT Q14 Q13 Q15 v Q1 CC v Q10 Q2 Q9 Q16 Q3 Q4 Q7 RBIAS VSS device Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 width m 96 96 48 48 96 96 96 144 144 24 96 96 48 12 48 12 RBIAS 15 k CC 2 0 pF length m 0 6 0 6 1 2 1 2 1 2 1 2 1 2 1 2 0 6 1 2 1 2 1 2 1 2 1 2 1 2 1 2 Complete the layout of this circuit observing the following points Q1 and Q2 should be drawn with common centroid geometry You should use the multi fingered gate common centroid layout as shown below though you may use different numbers of fingers and your widths and lengths will be different than in the figure Do not use the common centroid technique from the book D1 D2 Q2 15 1 M 4 Q1 15 1 M 4 G1 active G2 S poly G1 G2 S S D1 D2 S S D2 D1 S S G2 G1 Q15 should have exactly four times the width of Q16 same with Q13 to Q14 to ensure an accurate ratio See equation 5 107 in the book to see why this ratio is important for setting an accurate bias You should use 4 multiple transistors in parallel to achieve this Due to the finite lambda resolution in layout you may not be able to draw the exact widths listed above Come as close as you can Use high resistance poly2 electrode for RBIAS Assume a resistance of 1 24 k per square Make the resistor no narrower than 10 3 m Use a poly poly2 capacitor for CC Assume a capacitance of 800 aF m2 Connect the poly2 side to Q10 so that the parasitic poly substrate capacitance ends up at the drain of Q6 Q7 Your capacitance should be at least 2 0 pF For example 1 999 pF is not acceptable but 2 01 pF is acceptable All pMOS devices should have their wells connected to VDD except for Q9 which must be in its own well You must include at least one substrate tie connected to VSS If you decide to draw a multi fingered gate for a transistor remember to change the width and M multiplier in your schematic For example W 100 M 1 can be split into W 50 M 2 or W 25 M 4 etc Your complete op amp layout must be approximately square If your layout is not exactly square its area will be calculated by squaring its longest dimension horizontal or vertical Your layout must fit within a square 125 x 125 microns Your layout must contain zero DRC errors You must enable the following options in LVS verification when checking your layout o Select Compare FET Parameters o Select Compare Capacitor Parameters o Select Compare Resistor Parameters o De select Ignore FET Body Terminal All other options should be selected Turn in the following A printout of the circuit schematic that you drew in the Cadence Virtuoso schematic editor A printout of the layout Zoom in so your layout occupies the entire screen On this printout label the following items by hand in ink o vin vin and vout These should be metal wires connected to the appropriate transistors o RBIAS o CC o Q1 Q2 o The horizontal and vertical dimensions of your op amp layout in microns A printout of the layout zoomed in on Q1 and Q2 With ink mark the four parts of the common centroid layout as Q1a Q1b Q2a and Q2b A printout of the LVS output file showing that the layout exactly matches the schematic The five smallest layouts in 6720 and the three smallest layouts in 5720 will receive bonus points We may ask to check your layout This means we may ask you to show us your layout passing LVS and DRC in the Cade lab If your layout fails to pass LVS and DRC and you have claimed otherwise in the assignment you turned in you will receive a zero on the assignment