ECE CS 5720 6720 ECE CS 5720 6720 Analog IC Design Tutorial for Cadence Layout DRC LVS Layout Simulation In this tutorial you ll build an inverter in two different ways as a schematic and as layout You know how to simulate the inverter using an analog simulator After you design and simulate the schematic you will design layout for an inverter and simulate a circuit extracted directly from the layout You will be able to compare the two simulations and see how they differ You will also check the layout for design rules and check that the layout matches the schematic Layout consists of the mask designs for each layer that gets sent to the chip fabrication service Schematic Draw the Schematic of an Inverter in Virtuoso Schematic Editor and make a symbol Transistor Sizes W L p 3 0 0 6 and W L n 1 5 0 6 All in microns Body of pMOS is connected to Vdd and that of the nMOS is connected to Vss 1 ECE CS 5720 6720 Schematic test bench for the inverter Make a new schematic cell inverter test to test the inverter you designed as shown below Input voltage pulse of 1MHz V1 0V V2 5V Vdd 5 V Vss 0 V Run a transient analysis for 2 s and make sure your output looks okay Drawing the layout of a CMOS Inverter In this phase of the tutorial you ll draw the layout for an inverter in the Virtuoso tool You ll check for design rule violations and check that the extracted layout is the same circuit as the schematic You ll then simulate the circuit extracted from the layout and compare it with a simulation of the schematic you just drew In library manager click File New Cell View Select the library and the cell in which you made the inverter schematic Now select Tool as Virtuoso This would also set your View Name to layout Click OK 2 ECE CS 5720 6720 This will open two windows The Virtuoso Editing window where the layout will be drawn and the LSW Layer Select Window where you select the layers diffusion metal1 metal2 polysilicon etc to draw Note Before we start with the layout the display should be set as follows to facilitate layout for the current design rules Click on Options Display you will see this window Set the Minor spacing Major spacing X Snap Spacing and Y Snap Spacing as shown Click Apply and then OK 3 ECE CS 5720 6720 a To draw the layout of a N type Transistor 1 Click on the active green layer in the LSW window In the Virtuoso Layout Editor window press r to activate the Rectangle command Now you can draw a rectangle by selecting the start and end points of the rectangle Press k to activate the Ruler command You can click on one of the corners of the green rectangle to place the ruler and measure the sides Typing K will clear all rulers Remember that our N transistor in the inverter schematic had a W L of 1 5 m 0 6 m The width of the diffusion will be usually the same as the width of the transistors but the length of diffusion region has to account for the source drain diffusions and the gate length A general rule of the thumb is to have the length of the diffusion region to be 3 m Gate length Use the stretch command by pressing s and stretch the diffusion layer to be of the size 1 5 m x 3 6 m 4 ECE CS 5720 6720 2 Draw contacts black colored layer cc of 0 6 m x 0 6 m size to be overlapped by diffusion by at least 0 3 m on the outside edges as shown below Also draw Metal 1 layer blue colored layer metal1 to overlap the contacts by 0 3 m on all sides 3 Now draw the gate of the transistor by selecting poly red in color in the LSW window Note that the poly layer should have an overhang of 0 6 m 5 ECE CS 5720 6720 4 Now we have to surround the active region with nselect to make it n type diffusion Select nselect green outline in the LSW and wrap it around the active rectangle such that it extends beyond the active region by 0 6 m as shown below 6 ECE CS 5720 6720 Your NMOS transistor of W L 1 5 0 6 microns is done Note that we have not connected the body of this device to Vss the substrate b To draw the layout of a P Type Transistor Draw the P type transistor W L 3 m 0 6 m similarly The only difference apart from the sizes would be to use pselect instead of nselect so that we get p type diffusion The other change or rather addition would be put this entire device in n well 7 ECE CS 5720 6720 5 8 Draw a transistor similar to the N transistor for the increased width of 3 m following steps 1 to 3 In step 4 use pselect orange outline instead of nselect 9 Now place n well around this entire device so that it extends beyond the diffusion by 1 8 m in all directions 8 ECE CS 5720 6720 Now your PMOS transistor is also ready Again we have not yet connected the body of this device the n well to Vdd We are now set to put together these two devices to make an inverter 10 Select the entire N transistor and place it exactly below the P transistor such that there is a gap of at least 1 8 m between the n well and the diffusion of the N transistor 9 ECE CS 5720 6720 11 Join the gates of the P and the N transistor as well the drains of the two transistors by stretching the poly and metal1 respectively 10 ECE CS 5720 6720 12 Draw the supply lines for Vdd and Vss using Metal 1 such that the inverter is sandwiched between the two supply lines The line below the NMOS will be our Vss and that above PMOS will be our Vdd They are made wide to avoid electro migration issues 11 ECE CS 5720 6720 and ohmic voltage drops I made them 4 8 m wide Make sure that the metal1 strips one connecting the drains and other carrying the supply voltage are at least 0 9 m away 13 Now connect the sources of the two transistors to Vdd and Vss respectively Also create a contact on the common gate which is out input by placing a layer of metal1 cc and poly as shown in the figure Metal1 and poly should surround the contact by 0 3 m 12 ECE CS 5720 6720 14 Now label the different nodes on our layout that matches those on your schematic To do this click on Create Pin 13 ECE CS 5720 6720 You get the following window Enter the Terminal Name Select Display Pin Name Select …