ECE CS 5720 6720 Design Project Op Amp Design Due Tuesday April 13 by 6 00 pm Assignments turned in up to one day late will incur a 10 penalty and will not be eligible for bonus points In this project you will design lay out and simulate a high performance operational amplifier Your op amp must meet the following minimum performance specifications while driving a load of CL 20 pF A unity gain frequency ft of 600 kHz or greater A low frequency gain of 65 dB or greater A phase margin no smaller than 50 A power dissipation of 30 mW or less An input common mode range ICMR and output common mode range OCMR of 1V with no visible distortion of signals between these values A positive and negative slew rate of 0 3 V s or greater Your op amp must be constructed under the following constraints A layout that fits within a 220 m 220 m square The 20 pF load capacitor CL should not be included in your layout and should only be included in your simulation as this represents an external load While common centroid layout is generally a good idea for differential pair transistors in op amps it is not required in this assignment Minimum transistor width is 1 5 m Minimum transistor length is 0 6 m We are using an n well CMOS process This means that pMOS wells may be tied to any potential in the circuit e g tied to VDD tied to the source etc However the bodies of all nMOS transistors must be tied to VSS You do not have to build a bias generator Instead you are allowed one and only one dc current source somewhere in your circuit Note that the current from this source does count towards your total power dissipation Of course you don t have to have an ideal current source in your layout but you do have to have the diode connected transistor that serves as the input to the current mirror You may only use two dc voltage sources to power your circuit VDD and VSS The absolute value of each source is limited to 2 5 V so the largest power supply you can create is 2 5 Your power supply does not have to be symmetrical you could use VDD 2 0 V VSS 1 2 V if you wish If you need any bias voltages e g for cascode transistors you must create a circuit to supply them you cannot use additional dc voltage sources to supply bias voltages You must select one of the following performance metrics to optimize in your design High speed op amp Circuits will be judged on unity gain frequency Any circuit entered in this area also must have positive and negative slew rates greater than 20 V s Low power op amp Circuits will be judged on total power dissipation Small op amp Circuits will be judged on smallest layout area Layout area is measured as the area of the smallest rectangle that encompasses all the layout including layers such as n select well etc In order to prove that your op amp meets the minimum performance specifications listed above you must run the following simulations with the current source voltage supplies and 20 pF load capacitance added and include the specified plots in your report You must measure the open loop transfer function of your op amp with load You should use the technique discussed in the second op amp simulation assignment using the RC network with very large R and C Include in your report a Bode plot showing gain and phase vs frequency The frequency range should go low enough to show the low frequency gain before the first pole and high enough to show the unity gain frequency Please draw arrows on this plot by hand or otherwise showing the phase margin Label the dc gain unity gain frequency and phase margin on this plot Configure your op amp as a unity gain buffer connected to its load Apply a sine wave with a frequency of 1 kHz and an amplitude of 1 V so that the sine wave swings from 1 V to 1V to the input Include in your report a plot of the input and output vs time The time period should encompass 2 3 cycles of the sine wave Points will be deducted if you do not increase the number of points in the transient simulation e g by using conservative simulation mode so that the plot looks smooth Label the minimum and maximum output voltages Run a transient simulation with the op amp configured as a unity gain buffer connected to its load and its input tied to ground not VSS Observe the currents coming from VDD and VSS Include this plot labeling the value of dc current The simulation time should be at least 100 ms to allow any transient glitches to settle out With the op amp still configured as a unity gain buffer connected to its load apply a square wave with an amplitude of 1 V so that the square wave swings from 1 V to 1V to the input Find an appropriate frequency so that you can clearly observe and measure the slew rate at the output Include this plot of input and output labeling positive and negative slew rates Your report must contain the following 1 Cover page Use a copy of the cover sheet shown on the next page Fill in all the appropriate information Be sure to include units for all your performance metrics Make a copy of this cover page for your records 2 Labeled schematic Print or neatly draw a schematic of your op amp on a full page labeling in in and out Label each transistor with a different number e g Q1 Q2 etc so that you may reference specific transistors in your report and write the width and length of the device in microns beside each transistor in the format W L For example if you make a transistor with W 15 m and L 0 6 m you might write beside it Q8 15 0 6 This is the only time in this class I will let you get away with not using units 3 Layout A full page printout of your layout zoomed in so that your circuit fills the entire screen Label the x and y dimensions of your circuit in microns Also label in in out and the bias input Labeling by hand in ink is fine 4 LVS printout showing that the layout verifies against your schematic The rest of the brief report must be typed not hand written Cadence plots should be inserted into the document text as figures not attached as separate sheets 5 Design strategy State which performance metric you tried to optimize in your op amp design e g high speed low power etc and explain what circuit design strategies you used to accomplish this optimization For example did you try to minimize or maximize the W L ratios of certain transistors Did you try to minimize or maximize …