Systems I Datapath Design I Topics Sequential instruction execution cycle Instruction mapping to hardware Instruction decoding Overview How do we build a digital computer Hardware building blocks digital logic primitives Instruction set architecture what HW must implement Principled approach Hardware designed to implement one instruction at a time Plus connect to next instruction Decompose each instruction into a series of steps Expect that most steps will be common to many instructions Extend design from there Overlap execution of multiple instructions pipelining Later in this course Parallel execution of many instructions In more advanced computer architecture course 2 Y86 Instruction Set Byte 0 nop 0 0 halt 1 0 rrmovl rA rB 2 0 rA rB irmovl V rB 3 0 8 rB V rmmovl rA D rB 4 0 rA rB D mrmovl D rB rA OPl rA rB jXX Dest call Dest ret pushl rA popl rA 5 6 7 8 9 A B 1 2 3 0 rA rB 4 5 addl 6 0 subl 6 1 andl 6 2 xorl 6 3 jmp 7 0 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6 D fn rA rB fn 0 Dest Dest 0 0 rA 8 0 rA 8 3 Building Blocks fun Combinational Logic 0 MUX 1 Operate on data and implement control Store bits A L U Compute Boolean functions of inputs B Continuously respond to input changes Storage Elements A valA srcA Addressable memories valB Non addressable registers srcB Loaded only as clock rises A valW Register file B W dstW Clock Clock 4 Hardware Control Language Very simple hardware description language Can only express limited aspects of hardware operation Parts we want to explore and modify Data Types bool Boolean a b c int words A B C Does not specify word size bytes 32 bit words Statements bool a bool expr int A int expr 5 HCL Operations Classify by type of value returned Boolean Expressions Logic Operations a b a b a Word Comparisons A B A B A B A B A B A B Set Membership A in B C D Same as A B A C A D Word Expressions Case expressions a A b B c C Evaluate test expressions a b c in sequence Return word expression A B C for first successful test 6 SEQ Hardware Structure newPC PC valE valM Write back valM State Program counter register PC Condition code register CC Register File Memories Access same memory space Data Data memory memory Memory Addr Data valE Execute Bch CC CC aluA aluB Data for reading writing program data Instruction for reading instructions Instruction Flow Read instruction at address specified by PC Process through stages Update program counter ALU ALU valA valB srcA srcB dstA dstB Decode A B Register RegisterM file file E icode ifun rA rB valC Fetch valP Instruction Instruction memory memory PC PC increment increment PC 7 newPC SEQ Stages PC valE valM Write back valM Fetch Read instruction from instruction memory Data Data memory memory Memory Addr Data Decode Read program registers Execute valE Execute Bch CC CC aluA aluB Compute value or address valA valB Memory Read or write data icode ifun rA rB valC Fetch A B Register RegisterM file file E Write program registers PC srcA srcB dstA dstB Decode Write Back ALU ALU valP Instruction Instruction memory memory PC PC increment increment Update program counter PC 8 Instruction Decoding Optional 5 0 rA rB Optional D icode ifun rA rB valC Instruction Format Instruction byte icode ifun Optional register byte rA rB Optional constant word valC 9 Executing Arith Logical Operation OPl rA rB Fetch Memory Read 2 bytes Decode Read operand registers Execute 6 fn rA rB Perform operation Set condition codes Do nothing Write back Update register PC Update Increment PC by 2 Why 10 Stage Computation Arith Log Ops Fetch OPl rA rB icode ifun M1 PC rA rB M1 PC 1 valP PC 2 valA R rA valB R rB valE valB OP valA Read instruction byte Read register byte Set CC Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register Memory Write R rB valE Write back result back PC update PC valP Update PC Decode Execute Formulate instruction execution as sequence of simple steps Use same general form for all instructions 11 Executing rmmovl rmmovl rA D rB 4 0 rA rB Fetch Memory Read 6 bytes Decode Read operand registers Execute D Compute effective address Write to memory Write back Do nothing PC Update Increment PC by 6 12 Stage Computation rmmovl Fetch Decode Execute Memory Write back PC update rmmovl rA D rB icode ifun M1 PC rA rB M1 PC 1 valC M4 PC 2 valP PC 6 valA R rA valB R rB valE valB valC Read instruction byte Read register byte Read displacement D Compute next PC Read operand A Read operand B Compute effective address M4 valE valA Write value to memory PC valP Update PC Use ALU for address computation 13 Executing popl popl rA Fetch Memory Read 2 bytes Decode Read stack pointer Execute b 0 rA 8 Increment stack pointer by 4 Read from old stack pointer Write back Update stack pointer Write result to register PC Update Increment PC by 2 14 Stage Computation popl Fetch popl rA icode ifun M1 PC rA rB M1 PC 1 valP PC 2 Decode Execute Memory Write back PC update valA R esp valB R esp valE valB 4 valM M4 valA R esp valE R rA valM PC valP Read instruction byte Read register byte Compute next PC Read stack pointer Read stack pointer Increment stack pointer Read from stack Update stack pointer Write back result Update PC Use ALU to increment stack pointer Must update two registers Popped value New stack pointer 15 Summary Today Sequential instruction execution cycle Instruction mapping to hardware Instruction decoding Next time Control flow instructions Hardware for sequential machine SEQ 16