Systems I Datapath Design I Topics Sequential instruction execution cycle Instruction mapping to hardware Instruction decoding Overview How do we build a digital computer Hardware building blocks digital logic primitives Instruction set architecture what HW must implement Principled approach Hardware designed to implement one instruction at a time Plus connect to next instruction Decompose each instruction into a series of steps Expect that most steps will be common to many instructions Extend design from there Overlap execution of multiple instructions pipelining Later in this course Parallel execution of many instructions In more advanced computer architecture course 2 Y86 Instruction Set Byte 0 1 2 3 4 nop 0 0 halt 1 0 rrmovl rA rB 2 0 rA rB irmovl V rB 3 0 8 rB V rmmovl rA D rB 4 0 rA rB D mrmovl D rB rA OPl rA rB jXX Dest call Dest ret pushl rA popl rA 5 0 rA rB D 6 fn rA rB 7 fn 8 9 A B 0 Dest Dest 5 addl 6 0 subl 6 1 andl 6 2 xorl 6 3 jmp 7 0 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6 0 0 rA 8 0 rA 8 3 Building Blocks fun Combinational Logic A Compute Boolean functions of inputs Continuously respond to input changes Operate on data and implement control Storage Elements Store bits Addressable memories Non addressable registers Loaded only as clock rises A L U B 0 MUX 1 valA srcA A Register file valB srcB B valW W dstW Clock Clock 4 Hardware Control Language Very simple hardware description language Can only express limited aspects of hardware operation Parts we want to explore and modify Data Types bool Boolean a b c int words A B C Does not specify word size bytes 32 bit words Statements bool a bool expr int A int expr 5 HCL Operations Classify by type of value returned Boolean Expressions Logic Operations a b a b a Word Comparisons A B A B A B A B A B A B Set Membership A in B C D Same as A B A C A D Word Expressions Case expressions a A b B c C Evaluate test expressions a b c in sequence Return word expression A B C for first successful test 6 An Abstract Processor What does a processor do Consider a processor that only executes nops void be a processor unsigned int pc unsigned char mem while 1 char opcode mem pc assert opcode NOP pc pc 1 Fetch Decode Execute 7 An Abstract Processor Executes nops and absolute jumps void be a processor unsigned int pc unsigned char mem while 1 char opcode mem pc switch opcode case NOP pc case JMP pc int mem pc 1 Missing execute and memory access 8 SEQ Hardware Structure State Program counter register PC Condition code register CC Register File Memories Access same memory space Data for reading writing program data Instruction for reading instructions Instruction Flow PC Process through stages Update program counter valE valM Write back valM Data Data memory memory Memory Addr Data valE Execute Bch CC CC ALU ALU aluA aluB valA valB srcA srcB dstA dstB Decode Read instruction at address specified by PC newPC icode ifun rA rB valC Fetch A B Register RegisterM file file E valP Instruction Instruction memory memory PC PC increment increment PC 9 SEQ Stages Fetch newPC PC valE valM Write back valM Data Data memory memory Read instruction from instruction Memory memory Addr Data Decode Read program registers Execute valE Execute Bch CC CC aluA aluB Compute value or address valA valB Memory Read or write data icode ifun rA rB valC Write program registers PC Fetch Update program counter srcA srcB dstA dstB Decode Write Back ALU ALU A B Register RegisterM file file E valP Instruction Instruction memory memory PC PC increment increment PC 10 Instruction Decoding Optional 5 0 rA rB Optional D icode ifun rA rB valC Instruction Format Instruction byte icode ifun Optional register byte rA rB Optional constant word valC 11 Executing Arith Logical Operation OPl rA rB Fetch Memory Read 2 bytes Decode 6 fn rA rB Read operand registers Execute Do nothing Write back Update register PC Update Perform operation Increment PC by 2 Set condition codes Why 12 Stage Computation Arith Log Ops Fetch Decode Execute Memory Write back PC update OPl rA rB icode ifun M1 PC rA rB M1 PC 1 Read instruction byte Read register byte valP PC 2 valA R rA Compute next PC Read operand A valB R rB valE valB OP valA Set CC Read operand B Perform ALU operation Set condition code register R rB valE Write back result PC valP Update PC Formulate instruction execution as sequence of simple steps Use same general form for all instructions 13 Executing rmmovl rmmovl rA D rB 4 0 rA rB Fetch Memory Read 6 bytes Decode Read operand registers Execute D Compute effective address Write to memory Write back Do nothing PC Update Increment PC by 6 14 Stage Computation rmmovl Fetch Decode Execute Memory Write back PC update rmmovl rA D rB icode ifun M1 PC rA rB M1 PC 1 Read instruction byte Read register byte valC M4 PC 2 valP PC 6 valA R rA Read displacement D Compute next PC Read operand A valB R rB valE valB valC Read operand B Compute effective address M4 valE valA Write value to memory PC valP Update PC Use ALU for address computation 15 Executing popl popl rA Fetch Memory Read 2 bytes Decode Read stack pointer Execute b 0 rA 8 Increment stack pointer by 4 Read from old stack pointer Write back Update stack pointer Write result to register PC Update Increment PC by 2 16 Stage Computation popl Fetch Decode Execute Memory Write back PC update popl rA icode ifun M1 PC rA rB M1 PC 1 Read instruction byte Read register byte valP PC 2 valA R esp Compute next PC Read stack pointer valB R esp valE valB 4 Read stack pointer Increment stack pointer valM M4 valA R esp valE R rA valM Read from stack Update stack pointer Write back result PC valP Update PC Use ALU to increment stack pointer Must update two registers Popped value New stack pointer 17 Summary Today Sequential instruction execution cycle Instruction mapping to hardware Instruction decoding Next time Control flow instructions Hardware for sequential machine SEQ 18