Datapath Design IIExecuting JumpsStage Computation: JumpsExecuting callStage Computation: callExecuting retStage Computation: retComputation StepsComputation StepsComputed ValuesSEQ HardwareSummaryDatapath Design IIIFetch LogicFetch LogicFetch Control Logic in HCLFetch Control LogicDecode LogicA SourceE DestinationExecute LogicALU A InputALU OperationMemory LogicInstruction StatusMemory AddressMemory ReadPC Update LogicPC UpdateSEQ OperationSEQ Operation #2SEQ Operation #3SEQ Operation #4SEQ Operation #5SEQ Summary1Datapath Design IITopicsControl flow instructionsHardware for sequential machine (SEQ)Systems I2Executing JumpsFetchRead 5 bytesIncrement PC by 5DecodeDo nothingExecuteDetermine whether to take branch based on jump condition and condition codesMemoryDo nothingWrite backDo nothingPC UpdateSet PC to Dest if branch taken or to incremented PC if not branchjXX Dest 7fn DestXX XXfall thru:XX XXtarget:Not takenTaken3Stage Computation: JumpsCompute both addressesChoose based on setting of condition codes and branch conditionjXX Desticode:ifun  M1[PC]valC  M4[PC+1]valP  PC+5FetchRead instruction byteRead destination addressFall through addressDecodeBch  Cond(CC,ifun)ExecuteTake branch? Memory Writeback PC  Bch ? valC : valPPC updateUpdate PC4Executing callFetchRead 5 bytesIncrement PC by 5DecodeRead stack pointerExecuteDecrement stack pointer by 4MemoryWrite incremented PC to new value of stack pointerWrite backUpdate stack pointerPC UpdateSet PC to Destcall Dest 8 0DestXX XXreturn:XX XXtarget:5Stage Computation: callUse ALU to decrement stack pointerStore incremented PCcall Desticode:ifun  M1[PC]valC  M4[PC+1]valP  PC+5FetchRead instruction byteRead destination address Compute return pointvalB  R[%esp]DecodeRead stack pointervalE  valB + –4ExecuteDecrement stack pointerM4[valE]  valP MemoryWrite return value on stack R[%esp]  valE WritebackUpdate stack pointer PC  valCPC updateSet PC to destination6Executing retFetchRead 1 byteDecodeRead stack pointerExecuteIncrement stack pointer by 4MemoryRead return address from old stack pointerWrite backUpdate stack pointerPC UpdateSet PC to return addressret 9 0XX XXreturn:7Stage Computation: retUse ALU to increment stack pointerRead return address from memoryreticode:ifun  M1[PC] FetchRead instruction byte valA  R[%esp]valB  R[%esp]DecodeRead operand stack pointerRead operand stack pointervalE  valB + 4ExecuteIncrement stack pointervalM  M4[valA] MemoryRead return addressR[%esp]  valE WritebackUpdate stack pointer PC  valMPC updateSet PC to return address8Computation StepsAll instructions follow same general patternDiffer in what gets computed on each stepOPl rA, rBicode:ifun  M1[PC]rA:rB  M1[PC+1] valP  PC+2FetchRead instruction byteRead register byte[Read constant word]Compute next PCvalA  R[rA]valB  R[rB]DecodeRead operand ARead operand BvalE  valB OP valASet CCExecutePerform ALU operationSet condition code register Memory[Memory read/write] R[rB]  valE WritebackWrite back ALU result[Write back memory result] PC  valPPC updateUpdate PCicode,ifunrA,rBvalCvalPvalA, srcAvalB, srcBvalECond codevalMdstEdstMPC9Computation StepsAll instructions follow same general patternDiffer in what gets computed on each stepcall DestFetchDecodeExecuteMemoryWritebackPC updateicode,ifunrA,rBvalCvalPvalA, srcAvalB, srcBvalECond codevalMdstEdstMPCicode:ifun  M1[PC]valC  M4[PC+1]valP  PC+5valB  R[%esp]valE  valB + –4M4[valE]  valP R[%esp]  valE PC  valCRead instruction byte[Read register byte]Read constant wordCompute next PC[Read operand A]Read operand BPerform ALU operation[Set condition code reg.][Memory read/write] [Write back ALU result]Write back memory resultUpdate PC10Computed ValuesFetchicode Instruction codeifun Instruction functionrA Instr. Register ArB Instr. Register BvalC Instruction constantvalP Incremented PCDecodesrcA Register ID AsrcB Register ID BdstE Destination Register EdstM Destination Register MvalA Register value AvalB Register value BExecutevalE ALU resultBch Branch flagMemoryvalM Value from memory11SEQ HardwareKeyBlue boxes: predesigned hardware blocksE.g., memories, ALUGray boxes: control logicDescribe in HCLWhite ovals: labels for signalsThick lines: 32-bit word valuesThin lines: 4-8 bit valuesDotted lines: 1-bit valuesInstructionmemoryInstructionmemoryPCincrementPCincrementCCCCALUALUDatamemoryDatamemoryNewPCrBdstE dstMALUAALUBMem.controlAddrsrcA srcBreadwriteALUfun.FetchDecodeExecuteMemoryWrite backdata outRegisterfileRegisterfileA BMERegisterfileRegisterfileA BMEBchdstE dstM srcA srcBicode ifun rAPCvalC valPvalBvalADatavalEvalMPCnewPC12SummaryTodayControl flow instructionsHardware for sequential machine (SEQ)Next timeControl logic for instruction executionTiming and clocking13Datapath Design IIITopicsControl logic for instruction executionTiming and clockingSystems I14Fetch LogicPredefined BlocksPC: Register containing PCInstruction memory: Read 6 bytes (PC to PC+5)Split: Divide instruction byte into icode and ifunAlign: Get fields for rA, rB, and valCInstructionmemoryInstructionmemoryPCincrementPCincrementrBicode ifun rAPCvalC valPNeedregidsNeedvalCInstrvalidAlignAlignSplitSplitBytes 1-5Byte 015Fetch LogicControl LogicInstr. Valid: Is this instruction valid?Need regids: Does this instruction have a register byte?Need valC: Does this instruction have a constant word?InstructionmemoryInstructionmemoryPCincrementPCincrementrBicode ifun rAPCvalC valPNeedregidsNeedvalCInstrvalidAlignAlignSplitSplitBytes 1-5Byte 016Fetch Control Logic in HCL# Determine instruction codeint icode = [imem_error: INOP;1: imem_icode;];# Determine instruction functionint ifun = [imem_error: FNONE;1: imem_ifun;];InstructionmemoryInstructionmemoryPCSplitSplitByte 0imem_erroricode ifun17Fetch Control Logicpushl rAA 0rA8jXX Dest7fn Destpopl rAB 0rA8call Dest8 0Destrrmovl rA, rB2 0rA rBirmovl V, rB3 0 8rB Vrmmovl rA, D(rB)4 0rA rB Dmrmovl D(rB), rA5 0rA rB DOPl rA, rB6fn rA rBret 9 0nop 0 0halt 1 0pushl rAA 0rA8pushl rAA 0A 0rA8rA8jXX Dest7fn DestjXX Dest7fn7fn Destpopl rAB 0rA8popl rAB 0B 0rA8rA8call Dest8 0Destcall Dest8 08 0Destrrmovl rA, rB2 0rA rBrrmovl rA, rB2 02 0rA rBrA rBirmovl V, rB3 0 8rB Virmovl V, rB3 03 0 8rB8rB