Systems I Datapath Design II Topics Control flow instructions Hardware for sequential machine SEQ 1 Executing Jumps jXX Dest 7 fn fall thru XX XX Not taken target XX XX Taken Fetch Memory Read 5 bytes Increment PC by 5 Decode Do nothing Execute Dest Determine whether to take branch based on jump condition and condition codes Do nothing Write back Do nothing PC Update Set PC to Dest if branch taken or to incremented PC if not branch 2 Stage Computation Jumps Fetch jXX Dest icode ifun M1 PC Read instruction byte valC M4 PC 1 valP PC 5 Read destination address Fall through address Bch Cond CC ifun Take branch PC Bch valC valP Update PC Decode Execute Memory Write back PC update Compute both addresses Choose based on setting of condition codes and branch condition 3 Executing call call Dest return XX XX target XX XX Fetch Memory Read 5 bytes Increment PC by 5 Decode Read stack pointer Execute Dest 8 0 Decrement stack pointer by 4 Write incremented PC to new value of stack pointer Write back Update stack pointer PC Update Set PC to Dest 4 Stage Computation call call Dest icode ifun M1 PC Read instruction byte valC M4 PC 1 valP PC 5 Read destination address Compute return point valB R esp valE valB 4 Read stack pointer Decrement stack pointer Memory Write M4 valE valP R esp valE Write return value on stack Update stack pointer back PC update PC valC Set PC to destination Fetch Decode Execute Use ALU to decrement stack pointer Store incremented PC 5 Executing ret ret 9 0 return XX XX Fetch Memory Read 1 byte Decode Read stack pointer Execute Increment stack pointer by 4 Read return address from old stack pointer Write back Update stack pointer PC Update Set PC to return address 6 Stage Computation ret ret icode ifun M1 PC Read instruction byte valA R esp valB R esp valE valB 4 Read operand stack pointer Read operand stack pointer Increment stack pointer Memory Write valM M4 valA R esp valE Read return address Update stack pointer back PC update PC valM Set PC to return address Fetch Decode Execute Use ALU to increment stack pointer Read return address from memory 7 Computation Steps Fetch Decode Execute Memory Write back PC update icode ifun rA rB valC valP valA srcA valB srcB valE Cond code valM dstE dstM PC OPl rA rB icode ifun M1 PC rA rB M1 PC 1 valP PC 2 valA R rA valB R rB valE valB OP valA Set CC R rB valE PC valP Read instruction byte Read register byte Read constant word Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register Memory read write Write back ALU result Write back memory result Update PC All instructions follow same general pattern Differ in what gets computed on each step 8 Computation Steps Fetch Decode Execute Memory Write back PC update icode ifun rA rB valC valP valA srcA valB srcB valE Cond code valM dstE dstM PC call Dest icode ifun M1 PC valC M4 PC 1 valP PC 5 valB R esp valE valB 4 M4 valE valP R esp valE PC valC Read instruction byte Read register byte Read constant word Compute next PC Read operand A Read operand B Perform ALU operation Set condition code reg Memory read write Write back ALU result Write back memory result Update PC All instructions follow same general pattern Differ in what gets computed on each step 9 Computed Values Fetch icode ifun rA rB valC valP Decode srcA srcB dstE dstM valA valB Instruction code Instruction function Instr Register A Instr Register B Instruction constant Incremented PC Execute valE Bch ALU result Branch flag Memory valM memory Value from Register ID A Register ID B Destination Register E Destination Register M Register value A Register value B 10 SEQ Hardware newPC New PC PC Key valM data out Blue boxes predesigned hardware blocks Mem control Memory Gray boxes control logic White ovals labels for signals Thick lines 32 bit word values Thin lines 4 8 bit values Dotted lines 1 bit values write Execute Bch valE CC CC ALU ALU ALU A Describe in HCL Data Data memory memory Addr E g memories ALU read Data ALU fun ALU B valA valB dstE dstM srcA srcB dstE dstM srcA srcB Decode A icode Fetch B Register Register M file file E ifun rA rB Instruction Instruction memory memory valC Write back valP PC PC increment increment PC 11 Summary Today Control flow instructions Hardware for sequential machine SEQ Next time Control logic for instruction execution Timing and clocking 12 Systems I Datapath Design III Topics Control logic for instruction execution Timing and clocking 13 Fetch Logic icode ifun rA rB valC valP Need valC Instr valid Need regids Split Split PC PC increment increment Align Align Byte 0 Bytes 1 5 Instruction Instruction memory memory Predefined Blocks PC PC Register containing PC Instruction memory Read 6 bytes PC to PC 5 Split Divide instruction byte into icode and ifun Align Get fields for rA rB and valC 14 Fetch Logic icode ifun rA rB valC valP Need valC Instr valid Need regids Split Split PC PC increment increment Align Align Byte 0 Bytes 1 5 Instruction Instruction memory memory Control Logic PC Instr Valid Is this instruction valid Need regids Does this instruction have a register byte Need valC Does this instruction have a constant word 15 Fetch Control Logic in HCL icode ifun Split Split Byte 0 Determine instruction code int icode imem error INOP 1 imem icode imem error Instruction Instruction memory memory PC Determine instruction function int ifun imem error FNONE 1 imem ifun 16 Fetch Control Logic nop 0 0 halt 1 0 rrmovl rA rB 2 0 rA rB irmovl V rB 3 0 8 rB V rmmovl rA D rB 4 0 rA rB D mrmovl D rB rA 5 0 rA rB D OPl rA rB 6 fn rA rB jXX Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl rA A 0 rA 8 popl rA B 0 rA 8 bool need regids icode in IRRMOVL IOPL IPUSHL IPOPL IIRMOVL IRMMOVL IMRMOVL bool instr valid icode in INOP IHALT IRRMOVL IIRMOVL IRMMOVL IMRMOVL IOPL IJXX ICALL IRET IPUSHL IPOPL 17 Decode Logic valA valB A B valM valE Register File Read ports A B Write ports E M Addresses are register IDs or 8 no access dstE Register Register file file dstM srcA dstE dstM srcA srcB M E srcB Control Logic srcA srcB read port addresses dstA dstB write port addresses icode rA rB 18 A Source Decode OPl rA rB valA R rA Read operand A Decode rmmovl rA D rB valA R rA Read operand A Decode popl rA valA R esp Read stack pointer Decode Decode Decode jXX Dest No operand call Dest No operand ret valA R esp int srcA icode in IRRMOVL IRMMOVL IOPL IPUSHL icode in IPOPL IRET RESP 1 RNONE Don t need register Read stack pointer rA …