CS:APP2e CS:APP Chapter 4 Computer Architecture Instruction Set Architecture– 2 – CS:APP2e Instruction Set Architecture Assembly Language View  Processor state  Registers, memory, …  Instructions  addl, pushl, ret, …  How instructions are encoded as bytes Layer of Abstraction  Above: how to program machine  Processor executes instructions in a sequence  Below: what needs to be built  Use variety of tricks to make it run fast  E.g., execute multiple instructions simultaneously ISA Compiler OS CPU Design Circuit Design Chip Layout Application Program– 3 – CS:APP2e %eax %ecx %edx %ebx %esi %edi %esp %ebp ZF SF OF Y86 Processor State  Program Registers  Same 8 as with IA32. Each 32 bits  Condition Codes  Single-bit flags set by arithmetic or logical instructions » ZF: Zero SF:Negative OF: Overflow  Program Counter  Indicates address of next instruction  Program Status  Indicates either normal operation or some error condition  Memory  Byte-addressable storage array  Words stored in little-endian byte order RF: Program registers CC: Condition codes PC DMEM: Memory Stat: Program status– 4 – CS:APP2e Y86 Execution • Sequence of instructions • PC points to next instruction • Fetch & decode • Read instruction at PC • Execute • Update registers • Move values to/from memory • Update condition codes • Update PC • Default: next instruction • call/jmp instructions set new PC • goto considered your only option %eax %esi %ecx %edi %edx %esp %ebx %ebp addl %eax, %ecx irmovl $0x5, %ebx jmp $0xaddr2 call $0xfn_addr ZF SF OF– 5 – CS:APP2e Y86 Instruction Set #1 Byte 0 1 2 3 4 5 pushl rA A 0 rA 8 jXX Dest 7 fn Dest popl rA B 0 rA 8 call Dest 8 0 Dest rrmovl rA, rB cmovXX rA, rB 2 fn rA rB irmovl V, rB 3 0 8 rB V rmmovl rA, D(rB) 4 0 rA rB D mrmovl D(rB), rA 5 0 rA rB D OPl rA, rB 6 fn rA rB ret 9 0 nop 1 0 halt 0 0– 6 – CS:APP2e Y86 Instructions Format  1–6 bytes of information read from memory  Can determine instruction length from first byte  Not as many instruction types, and simpler encoding than with IA32  Each accesses and modifies some part(s) of the program state– 7 – CS:APP2e Y86 Instruction Set #2 Byte 0 1 2 3 4 5 pushl rA A 0 rA 8 jXX Dest 7 fn Dest popl rA B 0 rA 8 call Dest 8 0 Dest rrmovl rA, rB cmovXX rA, rB 2 fn rA rB irmovl V, rB 3 0 8 rB V rmmovl rA, D(rB) 4 0 rA rB D mrmovl D(rB), rA 5 0 rA rB D OPl rA, rB 6 fn rA rB ret 9 0 nop 1 0 halt 0 0 rrmovl 2 0 cmovle 2 1 cmovl 2 2 cmove 2 3 cmovne 2 4 cmovge 2 5 cmovg 2 6– 8 – CS:APP2e Y86 Instruction Set #3 Byte 0 1 2 3 4 5 pushl rA A 0 rA 8 jXX Dest 7 fn Dest popl rA B 0 rA 8 call Dest 8 0 Dest rrmovl rA, rB cmovXX rA, rB 2 fn rA rB irmovl V, rB 3 0 8 rB V rmmovl rA, D(rB) 4 0 rA rB D mrmovl D(rB), rA 5 0 rA rB D OPl rA, rB 6 fn rA rB ret 9 0 nop 1 0 halt 0 0 addl 6 0 subl 6 1 andl 6 2 xorl 6 3– 9 – CS:APP2e Y86 Instruction Set #4 Byte 0 1 2 3 4 5 pushl rA A 0 rA 8 jXX Dest 7 fn Dest popl rA B 0 rA 8 call Dest 8 0 Dest rrmovl rA, rB cmovXX rA, rB 2 fn rA rB irmovl V, rB 3 0 8 rB V rmmovl rA, D(rB) 4 0 rA rB D mrmovl D(rB), rA 5 0 rA rB D OPl rA, rB 6 fn rA rB ret 9 0 nop 1 0 halt 0 0 jmp 7 0 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6– 10 – CS:APP2e Encoding Registers Each register has 4-bit ID  Same encoding as in IA32 Register ID 15 (0xF) indicates “no register”  Will use this in our hardware design in multiple places %eax %ecx %edx %ebx %esi %edi %esp %ebp 0 1 2 3 6 7 4 5– 11 – CS:APP2e Instruction Example Addition Instruction  Add value in register rA to that in register rB  Store result in register rB  Note that Y86 only allows addition to be applied to register data  Set condition codes based on result  e.g., addl %eax,%esi Encoding: 60 06  Two-byte encoding  First indicates instruction type  Second gives source and destination registers addl rA, rB 6 0 rA rB Encoded Representation Generic Form– 12 – CS:APP2e Arithmetic and Logical Operations  Refer to generically as “OPl”  Encodings differ only by “function code”  Low-order 4 bytes in first instruction word  Set condition codes as side effect addl rA, rB 6 0 rA rB subl rA, rB 6 1 rA rB andl rA, rB 6 2 rA rB xorl rA, rB 6 3 rA rB Add Subtract (rA from rB) And Exclusive-Or Instruction Code Function Code– 13 – CS:APP2e Condition codes • Set with each arithmetic/logical op. • ZF: was the result 0? • SF: was the result <0? • OF: did the result overflow? (two’s complement) addl rA, rB 0x1,0x2 0,0,0 instruction values ZF,SF,OF addl rA, rB TMIN,-1 0,0,1 addl rA, rB 1,-2 0,1,0 addl rA, rB 5,-5 1,0,0 addl rA, rB TMIN,TMIN 1,0,1– 14 – CS:APP2e Move Operations  Like the IA32 movl instruction  Simpler format for memory addresses  Give different names to keep them distinct rrmovl rA, rB 2 0 rA rB Register --> Register Immediate --> Register irmovl V, rB 3 0 8 rB V Register --> Memory rmmovl rA, D(rB) 4 0 rA rB D Memory --> Register mrmovl D(rB), rA 5 0 rA rB D– 15 – CS:APP2e Move Instruction Examples irmovl $0xabcd, %edx movl $0xabcd, %edx 30 82 cd ab 00 00 IA32 Y86 Encoding rrmovl %esp, %ebx movl %esp, %ebx 20 43 mrmovl -12(%ebp),%ecx movl -12(%ebp),%ecx 50 15 f4 ff ff ff rmmovl %esi,0x41c(%esp) movl %esi,0x41c(%esp) — movl $0xabcd, (%eax) — movl %eax, 12(%eax,%edx) — movl (%ebp,%eax,4),%ecx 40 64 1c 04 00 00– 16 – CS:APP2e Conditional Move Instructions  Refer to generically as “cmovXX”  Encodings differ only by “function code”  Based on values of condition codes  Variants of rrmovl instruction  (Conditionally) copy value from source to destination register rrmovl rA, rB Move Unconditionally cmovle rA, rB Move When Less or Equal cmovl rA, rB Move When Less cmove rA, rB Move When Equal cmovne rA, rB Move When Not Equal cmovge rA, rB Move When Greater or Equal cmovg rA, rB Move When Greater 2 0 rA rB 2 1 rA rB 2 2 rA rB 2 3 rA rB 2 4 rA rB 2 5 rA …