CS APP Chapter 4 Computer Architecture Instruction Set Architecture CS APP2e Instruction Set Architecture Assembly Language View Processor state Registers memory Instructions addl pushl ret How instructions are encoded as bytes Layer of Abstraction Above how to program machine Processor executes instructions Application Program Compiler OS ISA CPU Design Circuit Design in a sequence Below what needs to be built Use variety of tricks to make it 2 run fast E g execute multiple instructions simultaneously Chip Layout CS APP2e Y86 Processor State RF Program registers eax esi ecx edx ebx edi esp ebp CC Condition codes Stat Program status ZF SF OF DMEM Memory PC Program Registers Same 8 as with IA32 Each 32 bits Condition Codes Single bit flags set by arithmetic or logical instructions ZF Zero SF Negative OF Overflow Program Counter Indicates address of next instruction Program Status Indicates either normal operation or some error condition 3 Memory Byte addressable storage array Words stored in little endian byte order CS APP2e Y86 Execution Sequence of instructions PC points to next instruction Fetch decode addl eax ecx eax esi irmovl 0x5 ebx ecx edi jmp 0xaddr2 edx esp ebx ebp Read instruction at PC Execute Update registers ZF call 0xfn addr SF OF Move values to from memory Update condition codes Update PC Default next instruction call jmp instructions set new PC goto considered your only option 4 CS APP2e Y86 Instruction Set 1 Byte 0 1 2 3 4 halt 0 0 nop 1 0 rrmovl rA rB cmovXX rA rB 2 fn rA rB irmovl V rB 3 0 8 rB V rmmovl rA D rB 4 0 rA rB D mrmovl D rB rA 5 0 rA rB D OPl rA rB 6 fn rA rB jXX Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl rA A 0 rA 8 popl rA 5 B 0 rA 8 5 CS APP2e Y86 Instructions Format 1 6 bytes of information read from memory Can determine instruction length from first byte Not as many instruction types and simpler encoding than with IA32 6 Each accesses and modifies some part s of the program state CS APP2e Y86 Instruction Set 2 Byte 0 halt 0 0 nop 1 0 rrmovl rA rB cmovXX rA rB irmovl V rB rmmovl rA D rB 1 2 3 4 2 fn rA rB 3 4 0 8 rB rrmovl 2 0 cmovle 2 1 cmovl 2 2 cmove 2 3 cmovne 2 4 cmovge 2 5 cmovg 2 6 5 V 0 rA rB D mrmovl D rB rA 5 0 rA rB OPl rA rB 6 fn rA rB jXX Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl rA A 0 rA 8 popl rA 7 B 0 rA 8 D CS APP2e Y86 Instruction Set 3 Byte 0 1 2 3 4 5 halt 0 0 addl 6 0 nop 1 0 subl 6 1 rrmovl rA rB cmovXX rA rB 2 fn rA rB andl 6 2 irmovl V rB 3 0 8 rB V xorl 6 3 rmmovl rA D rB 4 0 rA rB D mrmovl D rB rA 5 0 rA rB D OPl rA rB 6 fn rA rB jXX Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl rA A 0 rA 8 popl rA 8 B 0 rA 8 CS APP2e Y86 Instruction Set 4 Byte 0 halt 0 0 nop 1 0 rrmovl rA rB cmovXX rA rB 2 fn rA rB irmovl V rB 3 0 8 rB V rmmovl rA D rB 4 0 rA rB D mrmovl D rB rA OPl rA rB jXX Dest call Dest ret pushl rA popl rA 9 5 1 2 3 0 rA rB 4 5 jmp 7 0 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6 D 6 fn rA rB 7 fn 8 9 A B 0 Dest Dest 0 0 rA 8 0 rA 8 CS APP2e Encoding Registers Each register has 4 bit ID eax ecx edx ebx 0 1 2 3 esi edi esp ebp 6 7 4 5 Same encoding as in IA32 Register ID 15 0xF indicates no register 10 Will use this in our hardware design in multiple places CS APP2e Instruction Example Addition Instruction Generic Form Encoded Representation addl rA rB 6 0 rA rB Add value in register rA to that in register rB Store result in register rB Note that Y86 only allows addition to be applied to register data Set condition codes based on result e g addl eax esi Encoding 60 06 Two byte encoding First indicates instruction type Second gives source and destination registers 11 CS APP2e Arithmetic and Logical Operations Instruction Code Add addl rA rB Function Code 6 0 rA rB Refer to generically as OPl Encodings differ only by function code Subtract rA from rB subl rA rB Low order 4 bytes in first instruction word 6 1 rA rB And andl rA rB Set condition codes as side effect 6 2 rA rB Exclusive Or xorl rA rB 12 6 3 rA rB CS APP2e Condition codes Set with each arithmetic logical op ZF was the result 0 SF was the result 0 OF did the result overflow two s complement instruction ZF SF OF addl rA rB 0x1 0x2 0 0 0 addl rA rB TMIN 1 0 0 1 addl rA rB 1 2 0 1 0 addl rA rB 5 5 1 0 0 addl rA rB 13 values TMIN TMIN 1 0 1 CS APP2e Move Operations rrmovl rA rB Register Register 2 0 rA rB 3 0 8 rB V rmmovl rA D rB 4 0 rA rB D 5 0 rA rB D irmovl V rB mrmovl D rB rA Register Memory Memory Register Like the IA32 movl instruction Simpler format for memory addresses Give different names to keep them distinct 14 Immediate Register CS APP2e Move Instruction Examples IA32 Y86 Encoding movl 0xabcd edx irmovl 0xabcd edx 30 82 cd ab 00 00 movl esp ebx rrmovl esp ebx 20 43 movl 12 ebp ecx mrmovl 12 ebp ecx 50 15 f4 ff ff ff movl esi 0x41c esp rmmovl esi 0x41c esp 40 64 1c 04 00 00 movl 0xabcd eax movl eax 12 eax edx movl ebp eax 4 ecx 15 CS APP2e Conditional Move Instructions Move Unconditionally rrmovl rA rB 2 0 rA rB Refer to generically as cmovXX 2 1 rA rB Encodings differ only by function code Based on values of condition codes Variants of rrmovl instruction Move When Less or Equal cmovle rA rB Move When Less cmovl rA rB 2 2 rA rB Move When Equal cmove rA rB 2 3 rA rB Conditionally copy value Move When Not Equal cmovne rA rB 2 4 rA rB Move When Greater or Equal cmovge rA rB from source to destination register 2 5 rA rB Move When Greater cmovg rA rB 16 2 6 rA rB CS APP2e Jump Instructions Jump Unconditionally jmp Dest 7 0 Dest …