EE 271 HW03 Solution Due On 03 16 2022 10 Points Q1 Write the following design code and testbench Analyze the waveform exploring gtkwave Analyzer and post your screenshots for the simulation output and waveform output Test Bench P a g e 1 13 EE 271 HW03 Solution Due On 03 16 2022 15 Points Q2 a Write the Verilog code given below Verify your design by providing a simple testbench that covers all possible input combinations and displays the output b Replace the assign statements with Gate Level Modelling Provide the same testbench and cross verify your results with a The screenshot of codes testbench and gate level modelling output after simulation and waveforms will be the submission P a g e 2 13 EE 271 HW03 Solution Due On 03 16 2022 10 Points Q3 Design the following circuit using gate level modelling Use the test bench provided Provide Screenshots of output and waveform Hint The intermediate wires here are X and X P a g e 3 13 EE 271 HW03 Solution Due On 03 16 2022 P a g e 4 13 EE 271 HW03 Solution Due On 03 16 2022 P a g e 5 13 HW03 Solution Due On 03 16 2022 20 Points Q4 Write a design using Functions given the testbench to calculate the Factorial of a 3 bit number Simulation screenshot and Waveform expected P a g e 6 13 EE 271 EE 271 HW03 Solution Due On 03 16 2022 20 Points Q5 Write a program Write a program to calculate Quotient and Remainder using Tasks given the testbench Simulation and Waveform expected P a g e 7 13 EE 271 HW03 Solution Due On 03 16 2022 P a g e 8 13 EE 271 HW03 Solution Due On 03 16 2022 10 Points Q6 Write Verilog code to implement given Moore FSM and verify it using given testbench Screenshots of your design file simulation output and waveforms should be your submission Note Your waveforms must include clk clock rst reset In Out current state and Next State P a g e 9 13 EE 271 HW03 Solution Due On 03 16 2022 P a g e 10 13 EE 271 HW03 Solution Due On 03 16 2022 P a g e 11 13 EE 271 HW03 Solution Due On 03 16 2022 P a g e 12 13 EE 271 HW03 Solution Due On 03 16 2022 5 Points Q7 Write a program in Quartus Prime Lite to light up an LED 0 in the FPGA Board Working code Pin Assignment and a picture of your lit up FPGA with group name expected First create a new project QP Lite Then select your Board Then create a Verilog file with the module name same as the project name given while creating the project Then write the design code compile and select appropriate pins in Pin Planner Then synthesize and generate programming file Then open Program Device and select the DE10 Board and flash your program 5 Points Q8 What is a clock divider in Verilog Why is it used Explain in Brief A clock divider divides the clock signals to increase the clock time and decrease the clock frequency This is used to adjust the frequency of FPGA so that all the interfaced devices can synchronously communicate with each other It is also used when we want slower clock speeds for our design 5 Points Q9 Write a simple Arduino code for blink led Explain your code and the pinouts This code uses internal LED defined as LED BUILTIN which is hardwired to the digital pin 13 of the UNO Board Code under Void Loop turns ON the LED and wait for two seconds 2000ms to turn it OFF After another two seconds code again turns ON the LED and this process repeats in a loop P a g e 13 13