Code Generation for Embedded Processors Rainer Leupers University of Dortmund Dept of Computer Science 12 4422 1 Dortmund Germany email leupers43 Is12 cs uni dortmund de code is very important for embedded systems due to limited system on a chip memory sizes real time constraints of embedded applications and the need to minimize power consumption of mobile devices The following processor classes are common in embedded systems Abstract The increasing use of programmable processors as IP blocks in embedded system design creates a need for C C compilers capable of generating efficient machine code Many of today s compilers for embedded processors suffer from insufficient code quality in terms of code size and performance This violates the tight chip area and realtime constraints often imposed on embedded systems The reason is that embedded processors typically show architectural features which are not well handled by classical compiler technology This paper provides a survey of methods and techniques dedicated to efficient code generation for embedded processors Emphasis is put on DSP and multimedia processors for which better compiler technology is definitely required In addition some frontend aspects and recent trends in research and industry are briefly covered The goal of these recent efforts in embedded code generation is to Microcontrollers These are tailored for control intensive applications and typically show a CISC architecture Microcontrollers allow for a high code density but computational resources are usually very limited Examples are the 805 1 and 6502 CPUs RISC processors These show a load store architecture and a large file of general purpose registers Due to the simplified instruction set the most effective code optimization technique for RISCs is global register allocation 3 A well known example for RISC cores is the ARM family facilitate the step from assembly to high level language pro gramming of embedded systems so as to provide higherproductivity dependability and portability of embedded software DSP processors These are tuned for arithmetic intensive applications and allow for fast execution of DSP routines such as FIR filters or FFT This is achieved by dedicated hardware support e g multipliers and address generation units and DSP specific data path architectures DSPs exist in a very large variety of domainspecific architectures Major vendors include Texas Instruments Motorola Analog Devices and NEC 1 Introduction Due to the increasing complexity of embedded systems and availability of deep submicron VLSI technology there is a shift towards more abstract system specification and implementation methods Today s VHDL or Verilog based specification methods are step by step being replaced by C C based languages which offer both a convenient abstraction level and high simulation speed Examples are the SystemC I and SpecC 2 initiatives In addition hardware synthesis from C C is becoming common e g in products by Synopsys CoCentric and C Level Design C C also offer an ideal interface to software synthesis for embedded systems The building blocks of today s and future systems are complex intellectual property IP components or cores many of which are programmable processors Obviously this IP based implementation methodology requires compilers capable of mapping C specifications into assembly code for embedded processors This contribution mainly deals with eficient code generation for embedded processors Efficiency of the generated Multimediaprocessors These are a recent mixture of RISC and DSP processors They use the VLIW programming paradigm i e multiple functional units working in parallel with statically determined schedules Thus multimedia processors allow for very high performance however at the expense of tow code density and high power consumption Frequently there is support for vectorized SIMD instructions see section 3 Examples are the TI C6x 5 and the Philips Trimedia 6 families Application specificprocessors ASIPs are a compromise between off the shelf processors and ASICs They show application specific data paths which sometimes can be customized w r t register file sizes and word 173 1080 1820 00 10 00 0 2000 IEEE lengths In this case retargetable compilers are required see section 6 Examples of ASIPs are Tensilica s Xtensa RISC based 7 and the AMS Gepard core DSP based 81 are also performed at the intermediate representation IR level where complex source code constructs have already been split into a simple form such as three address code Note that in practice these processor classes may overlap e g a RISC processor might have DSP extensions and microcontrollers might have a general purpose register file In this paper we primarily deal with code generation for the latter three processor classes since these are the most challenging ones from a C compiler design viewpoint In fact current compilers for many standard DSPs and multimedia processors have been empirically shown to produce significantly less efficient code as much as 1000 overhead in terms of performance and code size as compared to hand optimized reference code 9 10 1 I 121 The reason is that their special instruction set architectures are not well exploited by conventional compiler technology Therefore a large part of the software for such processors still has to be developed in assembly language This implies time consuming programming extensive debugging and low code portability The requirements of short time tomarket and dependable code are obviously much better met by using C C instead of assembly The need for more efficient compilers for embedded processors has been recognized about a decade ago The purpose of this contribution is to provide a survey of important techniques that have been developed for embedded code optimization while also highlighting their key methodologies which reach beyond the scope of classical compiler technology for general purpose systems In the following three sections we give examples for code optimization techniques at different levels in the compilation flow reaching from source level section 2 to assembly level techniques section 4 In section 5 we briefly discuss compiler frontend related issues while sections 6 and 7 provide an overview of recent compiler trends in academia and industry Finally conclusions are given Address code transformation The high level address code transformation techniques described in 161 can be regarded as an extension of the