Page 1 1 CS6810 School of Computing University of Utah Virtual Memory Today’s topics: Virtual memory deeper look at memory hierarchy & management TLB’s for incresed speed and protection a few examples of approaches to date Midterm Review topics you should pay attention to 2 CS6810 School of Computing University of Utah Memory Hierarchy • 3 physical memory types caches – on chip SRAM main memory – off chip DRAM » fronted by a memory controller • lots of details later in the course – for now think slow disk – either SSD or HD » magnetic or slow NVRAM • details later for now thing SUPER SLOW • Common principle similar to multi-level caches miss here? » dig deeper 3 CS6810 School of Computing University of Utah Main Memory Organization • Familiar optimizations wider memory » make a main memory transaction look like a cache line • handled primarily by the memory controller bus width » actually a standard • wider & slower: JEDEC • skinnier and faster: RAMBUS pipeline » with synchronous DRAM’s • pipeline extended into DIMM and DRAM chips interleaved or phased memory » n slow banks – interleave return on higher bandwidth path/bus » ultimately the trick being used in DDR1, 2, 3, …. optimize for sequential memory accesses » capitalize on spatial locality similar to caches 4 CS6810 School of Computing University of Utah Hierarchy OptionsPage 2 5 CS6810 School of Computing University of Utah Striping/Interleaving • Different for disks ignore this for now • For caches and main memory exploit concurrency in banks 6 CS6810 School of Computing University of Utah Virtual Memory • Large virtual address space mapping mechanism to physical main memory » e.g. 64 bit virtual address space • smaller physical address – 36-40 bits common now • Multiple process management each process has a “private” and “protected” virtual address space » but share physical memory (caches and main memory) • trick is how to manage this private/protected illusion so it’s true • for caches – virtual indexed and tagged via address spaces between DRAM and disk » miss becomes a page or TLB fault • TLB is just a cache of recently used page table entries » block becomes a page or segment 7 CS6810 School of Computing University of Utah Page Relocation • Page table allows contiguous virtual addresses to be mapped in a non-contiguous fashion in main memory 8 CS6810 School of Computing University of Utah Difficulties • TLB is a cache usually highly associative » conflict miss penalty is huge since miss • is to main memory (~300 cycles) or disk (~10 msec) • Main memory has 2 masters cache line sized blocks move up in the hierarchy page sized blocks move down in the the hierarchy memory controller has to keep it straight » used to be on the Northbridge chipset » now moving on chip • 2 of them on Nehalem for examplePage 3 9 CS6810 School of Computing University of Utah Line vs. Page Differences • Replacement page fault handled by OS » time to access disk + context switch is large » hence more exotic replacement (LRU’ish) policy is tractable • Capacity cache size choice is unrelated to either physical or virtual address size physical address size specifies maximum main memory size » smaller is OK but mask exists to based on existing configuration virtual address size specifies the minimum swap space size » multiply by how many processes you’d like to be partially resident • What’s on the disk SWAP partition File system partitions 10 CS6810 School of Computing University of Utah 2 VM Styles: Main Memory • Pages are fixed size super-page options exist to increase TLB reach • Segments variable sized – hence base pointer and offset addressing 11 CS6810 School of Computing University of Utah VM’s & Same 4 Questions • Placement lower miss rates vs. complex placement » large miss penalty • choose low miss rate place anywhere – similar to fully associative cache but on a page granularity in main mem • Addressing pages via a page table » VPN PPN and catenate page offset • page table or TLB cache does translation • valid bit needed as a minimum to indicate presence in main mem segmentation » segment table • segment # offset in segment table – pointer to head of segment table required • lots of segments bigger segment table required 12 CS6810 School of Computing University of Utah VPN PPN Mapping BasicsPage 4 13 CS6810 School of Computing University of Utah Normal Page Tables • Size # entries = number of virtual pages • Role VPN PPN translation » enables page relocation still need status tags » valid » protection: priv’d, R, W, Xeq, … • Potential problem 64-bit virtual address space, 34 bit physical address & 4 KB page » page table has 252 entries • YOW that’s more than physical memory » ideas of how to fix this? 14 CS6810 School of Computing University of Utah Inverted Page Table • Make page table reflect what’s in physical memory use a hash mechanism » create index into inverted page table compare VPN with tag to make sure of the hit » similar to caches if you don’t find it you go to disk » double jeopardy • disk access to get the page table • disk access to get the page you want • plus update the IPT • The good bit caches miss rarely IPT miss is even more rare 15 CS6810 School of Computing University of Utah Page Policies • Replacement LRU best but same story – expensive hence “use” bit idea is employed » rarer OS wake up makes this closer to LRU than it is for caches » strategy • spend a few OS cycles to reduce miss rate and horrific page miss penalty • Write strategy always write back – so dirty bit required » write-through to disk is silly write buffering works as with caches » larger grain size larger buffer size » get the requested one first then do the write
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