Page 1 1 CS6810 School of Computing University of Utah Instruction Set Architecture ISA Today’s topics: • Note: desperate attempt to get back on schedule • we won’t cover all of these slides – use for reference • Risk vs. CISC • x86 does both • ISA influence on performance & complexity • some basic examples • fetch and decode issues 2 CS6810 School of Computing University of Utah ISA • What is it really? set of instructions THE HW/SW contract » compiler correctly translates source code to the ISA » assembler translates to relocatable binary » linker solidifies relocatables into object code » HW promises to do what the object code says upside » ISA provides “reasonable” SW abstraction of the HW » what is missing? downside » reverse compatible requirement “hide what you can” effect • Options fixed vs. variable length, instructions (RISC, CISC), memory modes, etc.Page 2 3 CS6810 School of Computing University of Utah Instruction Characteristics • Simple operation op-code • Operand addressing explicit – source address is explicit implicit – source address implied by the op code or architecture • Address target memory (CISC) vs. register (RISC) RISC exception: load and store, jumps and calls • # of operands – 0, 1, 2, 3 0 stack machine: pop 0, 1, or 2 then push result 1 single accumulator: acc acc OP address target 2 GPR machine: R[RS0] R[RS0] OP R[RS1] 3 GPR machine: R[RS0] R[RS1] OP R[RS2] 4 CS6810 School of Computing University of Utah What Instructions are Needed • Very few if you want to get bonkers PDP-0 had a 3-bit opcode field – what 8 would you pick? » hint: 1 was HALT Ivan’s 1 instruction computer only used MOVE » saves op-code bits since there’s only 1 and you don’t need to specify it explicitly • More normal – varies significantly with segment arithmetic and logical » choice of what data types to support » fused: MAC control: branch, jump, call, return, branch OS – ignore these for now string bit field manipulationPage 3 5 CS6810 School of Computing University of Utah ISA Affects Everything 6 CS6810 School of Computing University of Utah Classifying ISA’sPage 4 7 CS6810 School of Computing University of Utah Form and Function are Related 8 CS6810 School of Computing University of Utah Modern Choice - GPR • Why? lBM legacy to some extent – they were dominant at the right time compiler optimizations for GPR » simpler cost model so easier to evaluate options » register scheduling easier than memory operations » stack lost due to compilers • and JB who came from IBM to be CEO of Burroughs • the company went down the tubes in 3 years • not clear that stack machines deserved the bad rap they got in history • Platform independence if GPR’s dominate then it’s a bigger pain for the compilers to also handle something that is very different software lives forever and HW evolves very quickly • Compiler technology is still key to extracting the performance of the HW advanced today for the GPR worldPage 5 9 CS6810 School of Computing University of Utah Sample Comparison • Examine datapath and control strategies • Datapath assumptions for this example only direct addressing 8 bit opcode 16 bit registers 16 bit memory address field no byte or half-word to keep things simple » use 32-bit values simple tri-state bus as well • Control assumptions micro-code like here in reality implemented by FSM controller 10 CS6810 School of Computing University of Utah Instruction FormatsPage 6 11 CS6810 School of Computing University of Utah Things to note • Abbreviations IR – instruction register MAR – memory address register MDR – memory data register ALU – arithmetic and logical unit • Ridiculously simple example ignores many critical issues idea is to convey what gets built » and how to start thinking about an implementation 12 CS6810 School of Computing University of Utah Accumulator Datapath Note: this was the model used in the first stored program computers in the late 40’sPage 7 13 CS6810 School of Computing University of Utah Accumulator Control 14 CS6810 School of Computing University of Utah Stack DatapathPage 8 15 CS6810 School of Computing University of Utah Stack Control (over simplified) 16 CS6810 School of Computing University of Utah GPR DatapathPage 9 17 CS6810 School of Computing University of Utah GPR Control 18 CS6810 School of Computing University of Utah Text’s classification for ISA types • (# of memory operands, Max ALU operands)Page 10 19 CS6810 School of Computing University of Utah (0,3) Reg-Reg: Pro’s and Con’s • Pure RISC only load and store go to memory • Advantages: simple fixed length instruction » simplifies decode simple code generation simple cost model » since CPI for instructions will be known » exception is load store • and in today’s high frequency world some things are a little more iffy • Disadvantages high IC Imem footprint some instructions don’t need all of the instruction word bits » mem footprint 20 CS6810 School of Computing University of Utah (1,2)/(1,3) Reg-Mem P’s & C’s • Evolved RISC and old CISC – go figure? some new RISC machines » speculative loads » predicated or deferred loads • Pro’s no need to do a load before a use instruction format is still simple improved code density • Con’s source operands are not equivalent in (1,2) » 1 reg source value is destroyed with result value » memory address field needs to be bigger than register field » CPI varies for anything from memory: cache, main, disk??Page 11 21 CS6810 School of Computing University of Utah (3,3) mem-mem P’s and C’s • Ultimate gaggy CISC extinct now and likely to remain that way • Pro’s small instruction footprint? » not clear given need for 3 large addresses doesn’t waste a register for touch once data » register
View Full Document
Unlocking...