Page 1 1 CS6810 School of Computing University of Utah Solid State NVRAM Technologies Today’s topics: Flash, PCRAM, SONOS, FeRAM, MRAM, Probe Storage, NRAM, RRAM basically a survey of current (FLASH) and future technologies – they will be disruptive if they succeed 2 CS6810 School of Computing University of Utah Generic Taxonomy: V & NV • Volatile SRAM - 5 or 6 transistors per cell » fast but costly & power hungry » usage • on chip - caches, register files, buffers, queues, etc. • off chip usage now rare except in embedded space DRAM - 1 T & 1 C per cell (lots of details later in the term) » focus on density and cost/bit • too bad both power and delay properties are problematic » usage - main memory • EDRAM now moving on chip for large “last cache” duties » specialty parts for mobile systems • low-power • self-refresh • takes advantage of light usage » battery backed DRAM - common in data-centerPage 2 3 CS6810 School of Computing University of Utah NV • Traditional non-volatile Magnetic Disk » cheap » mixed use: file system and scratch CD, DVD » even cheaper per unit but less capacity » media and SW distribution, personal archival Tape » cheapest » archival storage Solid state » more spendy but faster • PROM in various flavors - now primarily masked on chip • FLASH has essentially taken over at the component level • new contenders are on the horizon however 4 CS6810 School of Computing University of Utah Some Observations • Bandwidth and Latency both are important » latency problems can be hidden to some extent » bandwidth problems are much harder to hide • Increasing the storage hierarchy depth conventional approach » big memories are slow » helps with fragmentation & BW issues • Yale vs. Harvard conflicts with power constraints now » moving lots of bits over long wires is energy expensive • Somewhat troubling how little mem_arch has changed in 60 years opportunityPage 3 5 CS6810 School of Computing University of Utah The Changing Landscape • Disruptive technologies SSD’s are on the market now » better in terms of performance » much worse in terms of cost/bit • hard to see a future where FLASH wins this race » longevity - open question all technologies have a life-span: tubes, core, transistors, … • New roles lots of cores, parallelism, and flakey components » manufacturing and operational variation back up often and checkpoint » NVRAM needed - checkpoints shouldn’t be volatile • ideal use = write-only • low energy fast writes - reads can be more expensive – inversion of the normal viewpoint multiple special memories - e.g. texture cache in GPU land 6 CS6810 School of Computing University of Utah NVRAM Alternatives Source: Pirovano ICMTD-2005Page 4 7 CS6810 School of Computing University of Utah Commercial Aspects: FLASH • Recent reports a bit more gloomy due to world economy issues • 2004 $16B - predicted $72B by 2012 NOR - 30% CAGR in ‘04, similar now but reports vary » 1 Gb and 2 Gb packages NAND - 70% CAGR in ‘04 but now down to ~20% » 8 - 64 Gb packages (3D) » needs a write controller • today it’s on the chip 8 CS6810 School of Computing University of Utah NOR vs. NAND Geometry Source: Micron NAND: 4F2 NOR: 10F2 DRAM: 6-8F2Page 5 9 CS6810 School of Computing University of Utah NAND vs. NOR Properties Source: Micron 10 CS6810 School of Computing University of Utah Flash Component Source: MicronPage 6 11 CS6810 School of Computing University of Utah NAND Trends Source: Shin, 2005 Symp. VLSI Ckts 12 CS6810 School of Computing University of Utah NAND vs. DRAM 2007 • DRAM 65 nm process 2 Gb on 100 mm2 die 1.94 Gb/cm2 • NAND SLC 56.7 nm process 4 Gb on 80.8 mm2 die 4.3 Gb/cm2 • NAND MLC (2 bits/cell) 56.7 nm process 8 Gb on 80.8 mm2 die 11 Gb/cm2Page 7 13 CS6810 School of Computing University of Utah What’s Wrong with FLASH? No problem unless You care about speed, power » Looks good when compared to disk except for price OR operate in write rarely land • There are some alternatives BUT They all have some downsides » Maturity, expense, density, market & investment, etc. » Scaling claims - just how real are they • Worth tracking since FLASH futures may not be bright IEDM 2005 Panel ==> run out of gas in 2010 likely? Vendors disagree of course • Question obvious market niche: thumb drives, cameras, etc. SSD and checkpoint storage role might be in doubt 14 CS6810 School of Computing University of Utah What’s Next? • Talk about likely future NVRAM candidates Ignore quantum and DNA soup like structures » Distant future maybe - near future unlikely » Note: fab ramp is as important as the devices Many have been around for a long time » Development to deployment is a long and rocky road • How they work focus Maybe more technology than a user cares about Hopefully aid awareness of what to look for as the technologies progress Architects must track technology trends • Try and assess where their future might lie Memory shapes the systems around it » A fact most architects have ignored to date » Von Neumann’s corollaryPage 8 15 CS6810 School of Computing University of Utah Flash (Hot Chips ‘04) Note - NAND read times haven’t changed in years Density improvement is excellent Source: Micron tutorial 16 CS6810 School of Computing University of Utah Known FLASH issues • Speed - slow writes OK, but 25 usec reads?? High voltage on both read and write create problems » Charge pump takes time » Jitter on bit lines requires lengthy settle margin Conclusion is that reads are unlikely to get much faster • Retention Thicker tunnel oxide (7-12nm) provides good retention, but » High voltage requirements create reliability issue. • Channel punch through, junction breakdown, etc. • Also increases the read and write energies • Scaling Concern over single defect memory loss limits vertical scaling High voltage also
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