1Lecture 26: Interconnection Networks• Topics: flow control, router microarchitecture2Packets/Flits• A message is broken into multiple packets (each packethas header information that allows the receiver tore-construct the original message)• A packet may itself be broken into flits – flits do notcontain additional headers• Two packets can follow different paths to the destinationFlits are always ordered and follow the same path• Such an architecture allows the use of a large packetsize (low header overhead) and yet allows fine-grainedresource allocation on a per-flit basis3Flow Control• The routing of a message requires allocation of variousresources: the channel (or link), buffers, control state• Bufferless: flits are dropped if there is contention for alink, NACKs are sent back, and the original sender hasto re-transmit the packet• Circuit switching: a request is first sent to reserve thechannels, the request may be held at an intermediaterouter until the channel is available (hence, not trulybufferless), ACKs are sent back, and subsequentpackets/flits are routed with little effort (good for bulktransfers)4Buffered Flow Control• A buffer between two channels decouples the resourceallocation for each channel• Packet-buffer flow control: channels and buffers areallocated per packet Store-and-forward Cut-through• Wormhole routing: same as cut-through, but buffers ineach router are allocated on a per-flit basis, not per-packetTime-Space diagramsH B B B TH B B B TH B B B T0 1 2 3 4 5 6 7 8 9 10 11 12 13 14CycleChannel0123ChannelH B B B TH B B B TH B B B T01235Virtual ChannelsBuffers BuffersFlits do not carry headers. Once a packet starts going over achannel, another packet cannot cut in (else, the receivingbuffer confuse the flits of the two packets). If the packet isstalled, other packets can’t use the channel.With virtual channels, the flit can be received into one of N buffers.This allows N packets to be in transit over a given physical channel.The packet must carry an ID to indicate its virtual channel.channelBuffers BuffersPhysical channelBuffers Buffers6Example• Wormhole:• Virtual channel:ABBA is going from Node-1 to Node-4; B is going from Node-0 to Node-5Node-1Node-0Node-5(blocked, no free VCs/buffers)Node-2 Node-3 Node-4idleidleABANode-1Node-0Node-5(blocked, no free VCs/buffers)Node-2 Node-3 Node-4BATraffic Analogy:B is trying to makea left turn; A is tryingto go straight; thereis no left-only lanewith wormhole, butthere is one with VC7Virtual Channel Flow Control• Incoming flits are placed in buffers• For this flit to jump to the next router, it must acquirethree resources: A free virtual channel on its intended hop We know that a virtual channel is free when thetail flit goes through Free buffer entries for that virtual channel This is determined with credit or on/off management A free cycle on the physical channel Competition among the packets that share aphysical channel8Buffer Management• Credit-based: keep track of the number of free buffers inthe downstream node; the downstream node sends backsignals to increment the count when a buffer is freed;need enough buffers to hide the round-trip latency• On/Off: the upstream node sends back a signal when itsbuffers are close to being full – reduces upstreamsignaling and counters, but can waste buffer space9Deadlock Avoidance with VCs• VCs provide another way to number the links such thata route always uses ascending link numbers2 1 01 2 32 1 01 2 32 1 01 2 32 1 0171819181716102 101 100101 102 103117118119118117116202 201 200201 202 203217218219218217216• Alternatively, use West-first routing on the1stplane and cross over to the 2ndplane incase you need to go West again (the 2ndplane uses North-last, for example)10Router Functions• Crossbar, buffer, arbiter, VC state and allocation,buffer management, ALUs, control logic• Typical on-chip network power breakdown: 30% link 30% buffers 30% crossbar11Router Pipeline• Four typical stages: RC routing computation: the head flit indicates the VC that it belongs to, the VC state is updated, the headers are examined and the next output channel is computed (note: this is done forall the head flits arriving on various input channels) VA virtual-channel allocation: the head flits compete for theavailable virtual channels on their computed output channels SA switch allocation: a flit competes for access to its outputphysical channel ST switch traversal: the flit is transmitted on the output channelA head flit goes through all four stages, the other flits do nothing in thefirst two stages (this is an in-order pipeline and flits can not jumpahead), a tail flit also de-allocates the VC12Router Pipeline• Four typical stages: RC routing computation: compute the output channel VA virtual-channel allocation: allocate VC for the head flit SA switch allocation: compete for output physical channel ST switch traversal: transfer data on output physical channelRC VA SA ST-- -- SA ST-- -- SA ST-- -- SA STCycle 1 2 3 4 5 6 7Head flitBody flit 1Body flit 2Tail flitRC VA SA ST-- -- SA ST-- -- SA ST-- -- SA STSA------STALL13Speculative Pipelines• Perform VA and SA in parallel• Note that SA only requires knowledgeof the output physical channel, not the VC• If VA fails, the successfully allocatedchannel goes un-utilizedRCVASAST-- SA ST-- SA ST-- SA STCycle 1 2 3 4 5 6 7Head flitBody flit 1Body flit 2Tail flit• Perform VA, SA, and ST inparallel (can cause collisionsand re-tries)• Typically, VA is the criticalpath – can possibly performSA and ST sequentially• Router pipeline latency is a greater bottleneck when there is little contention• When there is little contention, speculation will likely work well!• Single stage pipeline?RCVASA STSA STSA STSA ST14Recent Intel RouterSource: Partha Kundu, “On-Die Interconnects for Next-Generation CMPs”,talk at On-Chip Interconnection Networks Workshop, Dec 2006• Used for a 6x6 mesh• 16 B, > 3 GHz• Wormhole with VCflow control15Recent Intel RouterSource: Partha Kundu, “On-Die Interconnects for Next-Generation CMPs”,talk at On-Chip Interconnection Networks Workshop, Dec 200616Title•
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