1Texas A&M UniversityECEN 449 – Microprocessor System DesignMemories2Texas A&M UniversityObjectives of this Lecture Unit• Learn about different types of memories– SRAM/DRAM/CAM– Flash3Texas A&M UniversitySRAM –Static Random Access Memory4Texas A&M UniversitySRAM – Static Random Access Memory5Texas A&M UniversitySRAM function• When RowSelect = 1, cell can be written or read• Cell written by precharging bit/bit~ lines to required value– Write drivers more powerful than NOT gates• Cell read by comparing bit/bit~ lines6Texas A&M UniversityMulti-ported SRAM• Sometimes we want to read and write at the same time• For example, registers in a processor chip– Support 2 reads and 1 write at the same time• Add more bit and word lines.7Texas A&M UniversityDual Ported SRAM WordB LineBitB Line8Texas A&M UniversityDual Ported SRAM –Second Design9Texas A&M UniversityRegister cell – 2 Reads and 1 Write10Texas A&M UniversitySRAM 16 words, each word = 4bits11Texas A&M UniversityRegister File – 32 Registers –each 32 bits12Texas A&M UniversitySRAM –Access timing cycles13Texas A&M UniversityDRAM – Dynamic RAM14Texas A&M UniversityDRAM function• Charge on the capacitance remembers 1• Charge dissipates over time– Over time 1 becomes 0• Need to refresh memory• To read, Row Select = 1, charge is transferred to bit line– Capacitor discharged– Every read requires rewriting read value back15Texas A&M UniversityDRAM organization16Texas A&M UniversityDRAM organization• Must amplify small charge on cell cap many times to drive off-chip– Makes it slower than SRAM• Select which of millions of bits to read or write17Texas A&M UniversityDRAM organization• Typically Din, Dout combined into D pins• WrEn (WriteEnable) and OEn (Output Enable) distinguish whether Data pins are input or output– WrEn asserted, OEn deasserted D = Din (Write Cycle)– WrEn deasserted, OEn asserted D = Dout (Read cycle)• Column and Row addresses are serially input on address pins– Column Address Select (CAS), Row Address Select (RAS) lines used– RAS asserted => latch address as row address– CAS asserted => latch address as column address18Texas A&M UniversityDRAM Read Timing19Texas A&M UniversityDRAM Write Timing20Texas A&M UniversitySRAM/DRAM comparison• Speed– SRAM +, DRAM –– Use SRAM for cache, network buffers, etc.• Volatility– SRAM retains data while power is on– DRAM must be refreshed every few milliseconds• Cost– SRAM -, DRAM ++– Use DRAM for big, cheap memories• Overhead– SRAM +, DRAM – (due to refreshing and clocks)– Use SRAM for small memories, DRAM for big21Texas A&M UniversityContent Addressable Memory (CAM)• In normal memories, we access data stored at a particular address– We give the address as input, to write/read data• What if we want to access data by its contents?– Content addressable memories• Used extensively in network routers/switches• Look up CAM tutorial at http://www.pagiamtzis.com/pubs/pagiamtzis-jssc2006.pdf22Texas A&M UniversityExample use of CAMs –Network Router1Xxxx xxxx30010 010020010 000010011 1xxxNext Hop –Output PortDestination Address23Texas A&M UniversityExample use of CAMs –network routers• Given a destination address, we want to find which way to send the packet• The routing table as organized as shown • We want to match the contents of the routing table entries to the destination address to find the direction in which to send the packet• Addresses may be completely or partially specified – Don’t cares or a concise way of representing many addresses– Saves space in the routing table24Texas A&M UniversityBinary CAMs25Texas A&M UniversityCAM Cell26Texas A&M UniversityBinary CAMs• CAM can be designed as 10-Transistor cell– Storage cell = 6-transistor SRAM• Match line is precharged high• When the Content in the cell doesn’t match the data on the search lines, match line is discharged => no match27Texas A&M UniversityCAM architecture28Texas A&M UniversityCAM architecture• When a line matches, we can output the address or location of that content• When multiple entries match, output the first match– Gives priority to earlier entries29Texas A&M UniversityTernary CAM• In many applications, we need to store Don’t cares• Three states: 0, 1, X• Use two bits of actual storage to encode the three different values• For example, use 01 = 0, 10 = 1, 00 = X30Texas A&M UniversityTCAM Cell31Texas A&M UniversityTCAM• Precharge Match line high• When stored data matches search line –match line stays high– Otherwise, match line pulled low32Texas A&M UniversityPersistent memory• SRAM/DRAM lose memory when power is turned off• More persistent memory needed for several applications– Photos in a digital camera– Bootable code or settings on circuits• Flash memory used for these applications– Memory persists across power on/off cycles– Small size33Texas A&M UniversityFlash memory• Charge stored on an isolated conductor –called floating gate• Charge has no path to dissipate• The charge on the floating gate controls the current flowing between source and drain– Tells if a 1 or 0 is in the cell• To erase the cell, a reverse voltage is applied between the drain and the controlling gate– Charge is dissipated through tunneling34Texas A&M UniversityFlash Memory Cell35Texas A&M UniversityErasing Flash memory36Texas A&M UniversityMemory organizations37Texas A&M UniversitySingle word Memory Organization• Word typically = 32 bits or 4 bytes• Addresses normally for bytes• a31a30….a2a1a0 -- address bits a1a0 not used when accessing memoryData bus3032Address busByte 0 Byte 1 Byte 2 Byte 338Texas A&M UniversityWide Memory Organization• Memory is slow compared to cache/processor• There is normally locality in memory accesses– If you access location A, likely to access A+1, A+2…– Why not access multiple words at a time to reduce access times28128Address busWord 0 Word 1 Word 2 Word 3Data bus39Texas A&M UniversityInterleaved Memory Organization• Organize memory into banks• Each bank can be separately accessed• Data is distributed across multiple banks to increase parallelismAddress BusData Bus40Texas A&M UniversityInterleaved Memory Organization• Can keep multiple banks busy at the same time• Give address to first bank, then a different address to second bank…so on• Data accesses will be in different stages in different