Running Linux on a Xilinx XUP BoardJohn H. KelmJune 23, 2006AbstractA tutorial for b ooting a fully functional op erating sys tem based on the Linux 2.4kernel on a Xilinx University Program Virtex II-Pro based development board is pre-sented. Furthermore, we describe a reconfigurable hardware accelerator that can beaccessed directly by applications or via a character device driver.1 IntroductionThe Xilinx University Program (XUP) development board provides a rich environment inwhich students can gain an understanding of system on a chip (SoC) design, software-hardware codesign, computer architecture and digital logic design and synthesis. The boardis based on the Xilinx Virtex-II Pro field programmable gate array (FPGA), which has twoembedded PowerPC405 cores in addition to nearly 31,000 logic cells in which to synthesizethe necessary system c omponents and implement the students’ own hardware designs.Although it is possible to build interesting SoC designs on the XUP board and run themwith free-standing applications, doing so fails to exercise the full capabilities of the board.It is not only possible to build a fully functioning system on the Virtex-II Pro using oneof the embedded PowerPC cores, but to also run a full-fledged operating system on top ofthe reconfigurable hardware. This tutorial describes: synthesizing the hardware necessaryto boot Linux 2.4.26 on the XUP board; how to obtain, configure and compile the kernelto run on the board; how to boot a fully functioning operating system using the hardwareand kernel developed in the tutorial; and methods for connecting hardware accelerators tothe the XUP board.To exploit the potential of the XUP board with Linux we have incorporated a motionestimation hardware accelerator—used for fast encoding of digital movies—to demonstratethe potential of such a reconfigurable platform. This tutorial steps through the basic pro-cedure required to build a Block RAM (BRAM) based hardware accelerator that can beconnected to the On-Chip Memory (OCM) bus of the embedded PowerPC 405 core on theXUP board. Interfacing with the hardware accelerator synthesized in the reconfigurablelogic of the FPGA is covered briefly for direct methods using the mmap() system call. Fur-thermore, interfacing with the accelerator using a character device driver implementationunder the Linux 2.4 kernel is described.12 Hardware ConfigurationBooting Linux on the XUP board requires some familiarity with the Xilinx tool chain. Thistutorial assumes that the reader has already installed the Xilinx Embedded Developers Kit(EDK), Platform Studio and ISE. The entirety of our work was completed using EDK Ver-sion 7.1.01i; the methods and advice may or may not apply for other versions.2.1 Base System BuilderThe first step uses the Xilinx wizard—Base System Builder (BSB), a wizard provided in theEDK that is used to generate a basic hardware configuration on the XUP board—to buildthe files and integrate the components necessary to boot Linux on the XUP board. After thewizard is complete, the system is synthesizable, however unable to boot the Linux kernel;modifications to the environment created by the BSB must be made. The tutorial cov-ers the necessary augmentations of the Machine System Settings (MSS) file which containshigh-level configuration data, the Microprocessor Hardware Specification (MHS) file whichprovides the non-default mappings for the system components, and the User ConstraintsFile (UCF) which maps internal wire names to external pins on the chip.Go to the File menu, select the New Project submenu and select Base System Builder Step 1. . . menu item. The BSB wizard allows the selection of hardware components to add to thedesign. Select a location to place all the files, noting that there must be no spaces in thefile names referenced from within the Xilinx tools. Go to the next menu and select I wouldlike to create a new design. and continue. Select the board vendor as Xilinx, the boardname as XUP Virtex-II Pro Development System and the board revision as C. The boarddefinition files may need to be downloaded from Xilinx if not already installed.In the next menu select PowerPC cores (this tutorial does not make use of the MicroB- Step 2laze soft cores) and 100 MHz bus and processor clock frequencies. Disable all externalcaches by selecting NONE for both On–Chip Memory (OCM) drop–down boxes. Enablethe JTAG interface to the FPGA. The checkbox for Cache has no effect; it enables thecache from within the stand–alone application template created by the BSB which will notbe used by this tutorial. Proceed to the next window.Our current designs run the Processor Local Bus (PLB) at 100 MHz and the pro ce ssorat 300 MHz, but to keep the tutorial consistent with our original process and to ensureaccuracy 100 MHz clocks are rec omme nded. All external caches are disabled in the initialdesign as well. Data caches are not possible if a hardware accelerator is connecte d via theData Side OCM (DSOCM) as des cribed in Section 4.The following list covers what peripherals are chosen in the next three windows of the Step 3BSB—all should be interrupt driven except for the DDR memory controller:• RS232 UART 1 – OPB UART16550, Configure as UART 16550• Ethernet MAC – PLB ETHERNET, No DMA2• SysACE CompactFlash – OPB SYSACE• DDR 512MB 64Mx64 rank1 row13 col10 cl2 5 – PLB DDR• PS2 Ports – OPB PS2 DUAL REF• VGA FrameBuffer – PLB TFT CNTLR REFAll other peripherals are to be disabled.In the next window select 16KB of BRAM attached to the PLB BRAM controller. At Step 4least one BRAM must be present in the design for the hardware build syste m to functionprop e rly. The framebuffer may cause some systems to crash while generating BSPs andLibraries and may need to be added manually.The next menus relate to software and do not pertain to the system being built here. Step 5Disable any related options. Select None as default values for STDIN and STDOUT. Donot select any of the sample applications. The wizard will now build the system and thenecessary files are generated.2.2 ConfigurationThe BSB generates all the necessary files needed to build a functioning SoC on the Virtex-IIPro. However, the files generated by the BSB are incomplete and the following alterationsmust be made.DDR Clocks Go to the Projects menu, select Add/Edit Cores then s elec t the Param- Step 6eters tab. Under the dcm 1 entry confirm the following parameters are present. Add anyabsent