1Texas A&M UniversityECEN 449 – Microprocessor System DesignFPGAs and Reconfigurable ComputingSome of the notes for this course were developed using the course notes for ECE 412 from the University of Illinois, Urbana-Champaign2Texas A&M UniversityObjectives of this Lecture Unit• Get a feel for the different technologies that can be used to implement a design– Flavors of hardware technologies – Flavors of implementation methods• Understand the basics of how FPGAs work– So that the CAD tools in the lab make sense to you3Texas A&M UniversitySoftware, Custom Hardware or Reconfigurable Hardware?• When should we use software, “custom” hardware, or reconfigurable hardware?• Software based systems are easiest to implement– But there is a huge performance gap between software and hand-designed (custom) hardware systems– Often 100-to-1 ratio of performance (speed) or performance/area• But custom hardware systems not so good for general computing– Big design effort (time, cost) are barriers to implementation– Not practical to buy a new machine every time you want to run a different program• Reconfigurable systems offer best-of-both-worlds– Run-time programmability (in the field)– Hardware-level performance (although lower than custom hardware)– FPGAs and CPLDs are the vehicles for reconfigurable systems.4Texas A&M UniversityWhy is Hardware Faster Than Software?• Spatial vs. Temporal Computation– Processors divide computation across time, dedicated hardware divides across space – But dedicated hardware is hardwired for a specific task.t1t2ABCt1 = xt2 = t1 * At2 = t2 + Bt2 = t2 * t1y = t2 + CTemporal Computation* ** ++xABCSpatial Computationy = Ax + Bx + C2Y5Texas A&M UniversityWhy is Hardware Faster Than Software?• Specialization:– Instruction set may not provide the operations your program needs– Processors provide hardware that may not be useful in every program or in every cycle of a given program• Multipliers•Dividers • Instruction Memory– Processors need lots of memory to hold the instructions that make up a program and to hold intermediate results.• Bit Width Mismatches– In general, processors have a fixed bit width, and all computations are performed on that many bits• Multimedia vector instructions (MMX) a response to this6Texas A&M UniversitySo why not just use Hardware?• Dedicated hardware is – Dedicated (not flexible)– Takes long to design and develop (typical processor takes a handful of years to design, with design teams of a few hundred engineers)– This is expensive!– Only way to justify such an effort is if the customer demand guarantees high volume sales• So there is a strong need for a design approach which has performance comparable to dedicated hardware, with ease-of-programmability comparable to software.• Answer? Reconfigurable computing (FPGAs, CPLDs and their cousins)7Texas A&M UniversityGood Applications for Reconfigurable Computing• Data Parallelism– Execute same computations on many independent data elements– Pipeline computations through the hardware• Small and/or varying bit widths– Take advantage of the ability to customize the size of operators• Low-volume applications which require rapid design turn-around time and hardware-like speeds– Several telecom, DSP (filters), radar, genomics (DNA sequence matching), processor emulation, neural network and similar applications.8Texas A&M UniversityWill FPGAs Defeat CPUs?• Capacity: Instructions are very dense representation, logic blocks aren’t• Tools: Compilers for reconfigurable logic aren’t very good– Some operations are hard to implement on FPGAs– C-for-FPGA technology is improving fast, thoughOne approach to capacity is to exploit the 90-10 rule of software– Run the 90% of code that takes 10% of execution time on a conventional processor– Run the 10% of code that takes 90% of execution time on reconfigurable logic• But the temptation to merge the two worlds is real– Programmable-reconfigurable processors9Texas A&M UniversityA Peek Under the Hood• In the next few slides, we will peek under the hood of some of competing hardware based digital system design platforms• We will cover– Application Specific ICs (ASICs). • Examples are IP routing ICs• SSI/MSI/LSI/VLSI– Reconfigurable (also sometimes called programmable) ICs. •Examples are FPGAs, CPLDs– Full custom Integrated Circuits (ICs). • Examples are processors, GPUs, network processors, DSP processors.10Texas A&M University• Very high capacity today -- 10-100M transistors• Very high speed – 500MHz+– Integration– Specificity• Can use any design style below (or a hybrid)– Full Custom– Standard-cell (synthesized) – dominating methodology due to manufacturing considerations• Long fabrication time– Weeks-months from completed design to product• Only economical for high-volume parts– Making the masks required for fabrication is becoming very expensive, in the order of $1M per designApplication Specific Integrated Circuits11Texas A&M UniversityDeep Submicron Design Challenges• This slide discusses why ASICs are becoming less popular in recent times (compared to reconfigurable ICs)• Physical effects are increasingly significant– Parasitics, reliability issues, power management, process variation, etc. • Design complexity is high – Multi-functionality integration– Design verification is a major limitation on time-to-market• Cost of fabrication facilities and mask making has increased significantly12Texas A&M UniversityRapid Increase in Manufacturing CostSource: EETimes$50Process (um)2.0 … 0.8 0.6 0.35 0.25 0.18 0.13 0.10Single Mask cost ($K)1.5 1.5 2.5 4.5 7.5 12 40 60# of Masks12 12 12 16 20 26 30 34Mask Set cost ($K)18 18 30 72 150 312 1,000 2,0007.5124060$0.0$0.5$1.0$1.5$2.0$2.5250nm 180nm 130nm 100nmTotal Cost for Mask Set ($M)0$10$20$30$40$60Cost/Mask ($K)13Texas A&M UniversityThe Cost of Next Generation Product Source: IBS Inc.Wireless chip caseNetworking chip case0.18um0.13um90nm10203040500.15Total Product Cost ($M)$30M ~ $50M @ 90nmEngineering Cost – 60% upManufacturing Cost – 40% upNRE/Mask Cost – 100% upProductCostRespin cost – 78% up14Texas A&M UniversityProgrammable Logic Devices• Early version: Mask-Programmable Gate Arrays– Build standard layout of transistors on chip– Customer specifies wiring to connect transistors into gates/system– Only has to go through last few