Lab 2. Using Xilinx Platform System (XPS) Objective The aim of the lab is to become familiar with XPS, and use software (which will run on the PowerPC microprocessor on the FPGA) to control the LEDs. In lab1, we used hardware (using Verilog to program the FPGA to control the LEDs). In this lab, we will use software (C code running on the PowerPC), in order to control the LEDs. This lab is divided into two parts. The solutions to the problems at the end of Part A need to be submitted by the end of first week and the solutions to problems in Part B, by the end of the second week. Overview The block diagram for the complete system on the XUP board is shown in Figure 1. Figure 1. Complete System The system consists of two buses – the Peripheral Local Bus (PLB) and the On-chip Peripheral Bus (OPB). The PowerPC and PLB BRAM (Block RAM) controllers are connected to the PLB Bus. A PLB2OPB Bridge connects the PLB Bus to the OPB Bus. The peripherals are connected to the OPB Bus. Switches, push buttons, LEDs, etc are General Purpose input-output (GPIO) devices. PPC0 PLB Bus PLB2OPB PLB BRAM CntlrOPB BusPLB BRAM PLB BRAM CntlrPLB BRAM INTCGPIOTimerUARTGPIOLEDGPIOPush ButtonSwitchesPPC1Procedure Create an empty directory called ‘lab2’ (for example, in C:/449). In Step2, we will specify this directory as the location where all the project related files should be created and stored. PART A: Base System Builder (BSB): We will use the BSB to set up the design environment. 1. Launch XPS and create a new project Select Start → Programs → Xilinx Platform Studio 8.2i → Xilinx Platform Studio Alternatively, double click on the XPS icon on the desktop. The XPS window, prompting to create or open an exisiting project pops up as shown in Figure 2. Figure 2. Select Base System Builder Chose Base System Builder Wizard and click OK. 2. Select the path for ‘lab2’ directory followed by system.xmp in Project File.Figure 3. BSB 3. In the Select Board dialog, chose: Board Vendor: Xilinx Board Name: XUP Virtex-II Pro Development System Click Next.Figure 4. Select Board 4. Now, the Select Processor Dialog Box opens (shown in Figure 5). The XUP board is equipped with a PowerPC hard processor core as well as a MicroBlaze soft processor core. PowerPC is a hard processor core. It means that you don't have to use it, but you can't remove it. It is a part of the hardware of the chip. The Microblaze is a virtual microprocessor that is built by combining blocks of code called cores. You only use as much of the processor as you desire. We will be using PowerPC for our experiments. Select PowerPC and click Next. Figure 5. Select Processor5. Configure the processor using the following options: Reference Clock Frequency: 100 MHz This the external clock source on the board you are using. This clock will be used to generate the processor and bus clocks. The values of processor clock allowed may depend on the FPGA or board you are using because certain on-chip resources (Digital Clock Manager or DCM) may be required to perform clock division or multiplication. Let’s chose a processor clock frequency of 100MHz. Processor Clock Frequency: 100 MHz Bus Clock Frequency: 100 MHz JTAG Debug Interface: FPGA JTAG On-Chip Memory (OCM) – Data: NONE On-Chip Memory (OCM) – Instruction: NONEFigure 6. Configure PowerPC 6. Now, the ‘Configure IO interfaces’ dialog box appears. Check the RS232_Uart_1 option, and fill in as shown in Figure 7 (select 11520 as the Baud Rate). RS232 will be used to transfer the data from the host computer (the computer on which you are working right now!) to the PowerPC. Deselect Ethernet_MAC. In the next few windows, deselect all other peripherals till you reach plb_bram_if_ctrl_1.Figure 7. Configure IO interface RS232 7. Add PLB BRAM (see Figure 8). The PowerPC needs some memory, to store and run the software applications. We thus need to add a PLB_BRAM block. Figure 8. Add Internal Peripherals: PLB BRAM 8. In the Software Setup window, choose RS232_Uart_1 as the device for STDIN and STDOUT. Uncheck both Memory test and Peripheral selftest (If checked, they generate the software code for testing Memory and peripherals) under Sample Application selection. Click Next.Figure 9. Software Setup 9. In the screen that shows up, you will see a summary of the system you have created. Click Generate. Click Finish to finish generating the project and OK to start using XPS. Figure 10. System Created10. The Base System has been created. Click on Hardware → Generate Netlist. It may take several minutes. This will set up the hardware we have selected using the BSB. 11. Click or select Software → Generate Libraries and BSPs to generate libraries for the project. This will create header file in the directory ppc405_0/include. Now, explore your ‘lab2’ directory. The following directories should be present in your ‘lab2’ directory (a brief description of the files contained by each is provided; we would be modifying some of these, to achieve the desired functionality). • data (contains UCF file that stores pin location and timing constraints) • etc (contains option file for controlling ISE tools and command file for controlling FPGA configuration) • hdl (wrapper files for system, processor, and peripherals) • implementation (netlist files for peripherals) • pcores (repository for peripherals) • ppc405_0, ppc405_1 (software related files for the two PowerPCs) • synthesis (files resulting from synthesis) • _xps (option files for various point tools in EDK) In our lab exercises, we will understand and modify the ucf file in data directory, software files in ppc405_0 and user-defined hardware (Verilog) files in pcores directory. For Lab 2, we are not adding any Verilog code, the pcores directory will therefore be empty. Deliverables – Part A In the XPS window, you will see the ‘Project Information Area’ on the left and ‘System Assembly View’ on the right. 1. Demonstrate your base system to the TA [2 points] You need to turn in a laboratory report for this lab. This report should contain the information below. 2. From the ‘Addresses’ tab in the ‘System Assembly View’ window, note down the Base Address, High Address and size of RS232_Uart_1. Also, note the XPAR_RS232_UART_1_BASEADDR and XPAR_RS232_UART_1_HIGHADDR from the file xparameters.h in ppc405_0/include directory. [2 points] 3.