ECEN 449: Microprocessor System DesignDepartment of Electrical and Computer EngineeringTexas A&M UniversityProf. Peng LiTA: Andrew Targhetta(Lab exercise created by A Targhetta and P Gratz)Laboratory Exercise #3Creating a Custom Hardware IP and Interfacing it with SoftwareObjectiveThe purpose of lab this week is to familiarize you with the process of creating and importing a custom IPmodule for a MicroBlaze based system. We will be using the ‘Create and Import Peripheral Wizard’ in XPSin conjunction with ISE to develop a custom peripheral for performing integer multiplication. We will thenintegrate the integer multiplication peripheral into a microprocessor system and develop software to interactwith the peripheral using XPS. This lab serves as a simple hardware/software co-design example.System OverviewThe microprocessor system you will build in this lab is depicted in Figure 1. In place of the GPIO modules,utilized in the last lab, is a multiplication block, which represents the integer multiplication peripheral youwill create. The UART in Figure 1 will be used to connect the XUP board to the workstation computerwhich will display the output of software executing on the MicroBlaze processor. The software you willdevelop in this lab will provide proof of operation for your multiplication peripheral.12 Laboratory Exercise #3MicroBlaze ProcessorBRAM CntlrBRAM CntlrBlock RAMUARTRS232DebugiLBM dLBMJTAGPLBMultiplicationFigure 1: MicroBlaze System DiagramProcedure1. To begin, create the base system shown in Figure 1 using a similar configuration as last lab. We donot have the multiplication peripheral yet but will add that after we create it.(a) Create a folder for Lab 3 and open XPS as outlined in Lab 2.(b) Use the Base System Builder (BSB) to create a system similar to that which you built in Lab 2.Ensure a UART is the only peripheral your system contains (i.e. no Ethernet MAC, PCIExpress,etc.).(c) After the BSB completes, navigate to the ‘System Assembly View’ in XPS. Then click on the‘Addresses’ tab. Change the size field on both the dlmb cntrl and the ilmb cntrl to 128K. Hit‘Generate Addresses’ to regenerate the address ranges of the other components on the bus.2. At this point, we should have everything in Figure 1 except for the multiplication peripheral. The next2 ECEN 449Laboratory Exercise #3 3few steps will guide you through the process of creating a custom IP peripheral. For today’s lab, ourcustom peripheral will have three software accessible 32-bit registers and a hardware multiplicationblock. Two of the software registers will be read and write accessible by the microprocessor and willhold the multiplicand and multiplier. The third register will be read accessible by the microprocessorand write accessible by the multiplication logic within the peripheral. The third register will hold theproduct of the multiplication.(a) From the XPS main menu, select Hardware→Create or Import Peripheral. The ‘Create andImport Peripheral Wizard’ should come up (Figure 2). Hit ‘Next’ to continue.Figure 2: Create and Import Peripheral Wizard - Welcome(b) The next window allows us to either create templates for a new peripheral or import an existingperipheral. Ensure ‘Create templates for a new peripheral’ is selected and leave ‘Load an existing.cip settings file’ unchecked. Press ‘Next’ to continue.(c) The window that follows gives us the option to store our peripheral design files in a location otherthan our current XPS project directory. Leave everything as default and hit ‘Next’ to continue.(d) A window will appear prompting you to assign a name and version number to your peripheral(Figure 3). Name the peripheral ‘multiply’ and leave the version number as default (i.e. 1.00.a).You can enter a short description of your peripheral if you would like in the ‘Description’ win-dow.ECEN 449 34 Laboratory Exercise #3Figure 3: Peripheral Name and Version(e) The next window allows us to select which bus we would like our peripheral to connect to.We want to connect to the PLB as the On-chip Peripheral Bus(OPB) has been phased out byXilinx. Ensure ‘Processor Local Bus (PBL v4.6)’ is selected and ‘Enable OPB and PLB v3.4bus interfaces’ is unchecked. Press ‘Next’ to move forward.(f) Figure 4 shows the next prompt. On the left, Xilinx provides us with a block diagram of ourperipheral and the various functionality it can have. The right hand side of the window allowsus to choose the services or functionality for our peripheral. Our peripheral is very simple andwill only have software accessible registers. Thus, ensure only ‘User logic software registers’ isselected and press ‘Next’ to proceed.(g) For the next window, leave everything as default. The ‘Burst and cache-line support’ option isfor high performance data transfer, which is unnecessary for our current application.(h) In the window that follows, set the ‘Number of software accessible registers’ field to 3. This willcause XPS to autogenerate the portion of our logic required to interface with the bus. Includedin that logic is the instantiation the three registers along with the sequential logic for readingand writing to those registers from the PLB. Hit ‘Next’ to move to the ‘IP Interconnect (IPIC)’portion of the wizard.(i) Examine the IPIC window. It provides us with a listing of the signals from the PLB, whichwill be connected to our peripheral. It also allows us to trim out any extraneous signals from4 ECEN 449Laboratory Exercise #3 5Figure 4: Peripheral configurationour logic. Until you have a better idea of what is going on, leave everything as default in thiswindow.(j) The subsequent window provides us with the option of generating a Bus Functional Model(BFM). For more complicated peripherals, BFMs are quite handy, allowing one to simulatetransactions on the PLB without simulating a microprocessor. For our simple design, a BFMis not necessary, and we do not have the required components installed anyway. Leave the‘Generate BFM simulation platform for ModelSim-SE or ModelSim-PE’ unchecked and press‘Next’ to continue.(k) In the ‘Peripheral Implementation Support’ window that follows, select all three check boxes.The first option causes XPS to autogenerate portions of peripheral logic in Verilog, while thesecond option causes XPS to create project directories and files for designing the remaining userlogic in ISE. The last option instructs XPS