# RIT EECC 341 - Study Notes (113 pages)

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## Study Notes

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- Pages:
- 113
- School:
- Rochester Institute of Technology
- Course:
- Eecc 341 - Introduction to Digital Systems for Computer Engineering

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Final Exam Review Combinational Logic Building Blocks Decoders Encoders Multiplexers Demultiplexers Implementing functions using decoders multiplexers Combinational Arithmetic Circuits Adders Subtractors Multipliers Comparators shifters Sequential Logic Circuits Latches Flip Flips Clocked Synchronous State Machines State Machine Analysis State Machine Design Registers Counters EECC341 Shaaban 1 Final Review Winter 2001 2 20 2002 Binary n to 2n Decoders A binary decoder has n inputs and 2n outputs Only the output corresponding to the input value is equal to 1 n inputs n to 2n decoder 2n outputs EECC341 Shaaban 2 Final Review Winter 2001 2 20 2002 3 to 8 Binary Decoder Truth Table F0 x y z x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z F0 F1 F2 F3 F4 F 5 F6 F7 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 F1 x y z F2 x yz F3 x yz F4 xy z F5 xy z F6 xyz F0 F7 xyz F1 X Y Z 3 to 8 Decoder F2 F3 F4 F5 F6 x y z F7 EECC341 Shaaban 3 Final Review Winter 2001 2 20 2002 Implementing Functions Using Decoders Any n variable logic function in canonical sum of minterms form can be implemented using a single n to 2n decoder to generate the minterms and an OR gate to form the sum The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate Any combinational circuit with n inputs and m outputs can be implemented with an n to 2n decoder with m OR gates Suitable when a circuit has many outputs and each output function is expressed with few minterms EECC341 Shaaban 4 Final Review Winter 2001 2 20 2002 Implementing Functions Using Decoders Example Full adder S x y z 1 2 4 7 C x y z 3 5 6 7 3 to 8 0 Decoder 1 x S2 y S1 z S0 2 3 4 5 6 7 x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 C 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1 S C EECC341 Shaaban 5 Final Review Winter 2001 2 20 2002 Encoders If the a decoder s output code has fewer bits than the input code the device is usually called an encoder e g 2n to n priority encoders The simplest encoder is a 2n to n binary encoder where it has only one of 2n inputs 1 and the output is the n bit binary number corresponding to the active input For an 8 to 3 binay encoder with inputs I0 I7 the logic expressions of the outputs Y0 Y2 are Y0 I1 I3 I5 I7 Y1 I2 I3 I6 I7 Y2 I4 I5 I6 I7 2n inputs Binary encoder n outputs EECC341 Shaaban 6 Final Review Winter 2001 2 20 2002 8 to 3 Binary Encoder At any one time only one input line has a value of 1 Inputs I0 1 0 0 0 0 0 0 0 I1 0 1 0 0 0 0 0 0 I2 0 0 1 0 0 0 0 0 I3 0 0 0 1 0 0 0 0 I4 0 0 0 0 1 0 0 0 Outputs I5 0 0 0 0 0 1 0 0 I6 0 0 0 0 0 0 1 0 I7 0 0 0 0 0 0 0 1 y2 0 0 0 0 1 1 1 1 y1 0 0 1 1 0 0 1 1 y0 0 1 0 1 0 1 0 1 I0 I1 Y2 I4 I5 I6 I7 I2 I3 y1 I2 I 3 I6 I 7 I4 I5 I6 I7 Y0 I1 I3 I5 I7 EECC341 Shaaban 7 Final Review Winter 2001 2 20 2002 Multiplexers A multiplexer MUX is a digital switches which connects data from one of n sources to the output A number of select inputs determine which data source is connected to the output Enable 1Y D0 Multiplexer EN s bits Select 2Y SEL Data output b bits D0 b bits D1 n Data Sources b bits Y D1 bY Dn 1 Dn 1 SEL EN EECC341 Shaaban 8 Final Review Winter 2001 2 20 2002 4 to 1 MUX Truth table for a 4 to 1 multiplexer I0 d0 d0 d0 d0 I1 d1 d1 d1 d1 I2 d2 d2 d2 d2 I3 d3 d3 d3 d3 S1 0 0 1 1 S0 0 1 0 1 Y d0 d1 d2 d3 Inputs I0 I1 I2 I3 S1 0 0 1 1 S0 0 1 0 1 Y I0 I1 I2 I3 Inputs 0 4 1 1 MUX Y 2 3 S1 S 0 I0 I1 Output I2 mux Y I3 S1 S 0 select select EECC341 Shaaban 9 Final Review Winter 2001 2 20 2002 4 to 1 MUX Circuit I0 I0 I1 I1 Y I2 Y I2 I3 I3 0 1 2 3 2 to 4 Decoder S1 S0 S1 S0 EECC341 Shaaban 10 Final Review Winter 2001 2 20 2002 Larger Multiplexers Larger multiplexers can be constructed from smaller ones An 8 to 1 multiplexer can be constructed from smaller multiplexers as shown I0 I1 I2 I3 4 1 MUX S1 S 0 I4 I5 I6 I7 4 1 MUX 2 1 MUX S2 Y S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Y I0 I1 I2 I3 I4 I5 I6 I7 S1 S 0 EECC341 Shaaban 11 Final Review Winter 2001 2 20 2002 Larger Multiplexers A 16 to 1 multiplexer can be constructed from five 4 to 1 multiplexers EECC341 Shaaban 12 Final Review Winter 2001 2 20 2002 Demultiplexers Digital switches to connect data from one input source to one of n outputs Usually implemented by using n to 2 n binary decoders where the decoder s enable line is used for data input of the demultiplexer Demux b bits Select Data Input One of n Data Sources selected Select lines b bits b bits One of n outputs s bits 2X4 Decoder Input data 1bit One of four 1 bit outputs Enable 1 bit 4 output demultiplexer using a 2x4 binary decoder EECC341 Shaaban 13 Final Review Winter 2001 2 20 2002 1 to 4 Demultiplexer Outputs Y0 D S1 S0 Y1 D S1 S0 Data D demux Y2 D S1 S0 Y3 D S1 S0 S1 So 0 0 0 1 1 0 1 1 Y0 D 0 0 0 Y1 0 D 0 0 Y2 0 …

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