Final Exam ReviewBinary n-to-2n Decoders3-to-8 Binary DecoderImplementing Functions Using DecodersSlide 5Encoders8-to-3 Binary EncoderMultiplexers4-to-1 MUX4-to-1 MUX CircuitLarger MultiplexersSlide 12Demultiplexers1-to-4 DemultiplexerImplementing n-variable Functions Using 2n-to-1 MultiplexersExample: 3-variable Function Using 8-to-1 muxImplementing n-variable Functions Using 2n-1-to-1 MultiplexersExample: 3-variable Function Using 4-to-1 muxCombinational Arithmetic CircuitsFull AdderFull Adder Circuit Using AND-ORn-bit Carry Ripple Adders4-bit Carry Ripple AdderLarger AddersCarry Look-Ahead AddersSlide 26Carry Look-Ahead CircuitBinary Arithmetic Operations SubtractionFull SubtractorFull Subtractor Circuit Using AND-ORn-bit Subtractors4-bit Borrow Ripple Subtractor4-bit Subtractor Using 4-bit AdderBinary Multiplication4x4 Array MultiplierCombinational ComparatorsExample: 4-bit ComparatorCombinational Shift CircuitsExample: Combinational 8-Bit Right ShifterSequential Logic CircuitsSequential Circuit Buliding Blocks: Generic Memory ElementsSequential Circuit Memory Elements: Latches, Flip-FlopsSlide 43S-R LatchS-R Latch With EnableD-LatchEdge-Triggered D Flip-FlopMaster/Slave S-R Flip-FlopMaster/Slave J-K Flip-FlopEdge Triggered J-K Flip-FlopT Flip-Flop With EnableClocked Synchronous State-MachinesClocked Synchronous State-Machine ModelLatch/Flip-Flop Characteristic EquationsClocked Synchronous State-machine AnalysisState DiagramState Machine Analysis ExampleSlide 58Slide 59Clocked State-machine Analysis: State NamingClocked State-machine Analysis Example: Transition/Output Table Using State NamesClocked State-machine Analysis Example: State Diagram Using State NamingClocked State-machine Analysis: State Machine Timing DiagramState Machine Timing Diagram ExampleState Machine Analysis Example 2Slide 66Slide 67State-machine Analysis Example 2: Transition/Output Table Using State NamesState-machine Analysis Example 2: State Diagram (incomplete)State Machine Analysis Example 3Slide 71Slide 72State-machine Analysis Example 3: Transition/Output Table Using State NamesState-machine Analysis Example 3: State DiagramState Machine Design ProcedureState Machine Design Example 1: 110 DetectorState Machine Design Example 1: 110 Detector Step1: Choosing StatesState Machine Design Example 1: 110 Detector Step 1: State/Output Table and DiagramStep3: State Assignment ConsiderationsState Assignment StrategiesExample: State Assignment StrategiesState Assignment Heuristic GuidelinesState Machine Design Example 1: 110 Detector Step 3: State AssignmentState Machine Design Example 1: 110 Detector Step 4: Transition/Output TableState Machine Design Example 1: 110 Detector Steps 7, 8 : Excitation/Output EquationsState Machine Design Example 1: 110 Detector Step 9: Logic DiagramState Machine Design Example 2: 110/101 DetectorState Machine Design Example 2: 110/101 Detector Step1: Choosing StatesState Machine Design Example 2: 110/101 Detector Step 1: State/Output TableState Machine Design Example 2: 110/101 Detector Step 1: State DiagramState Machine Design Example 2: 110/101 Detector Steps 3: State AssignmentState Machine Design Example 2: 110/101 DetectorState Machine Design Example 2: 110/101 Detector Steps 7: Excitation EquationsState Machine Design Example 2: 110/101 Detector Step 8: Output EquationsState Machine Design Using J-K Flip-FlopsState Machine Design Example 1: 110 Detector (Repeated Using J-K Flip-Flops)Slide 97State Machine Design Example 1: 110 Detector Using J-K Flip-flopsState Machine Design Example 1: 110 Detector Using J-K FF Steps 7, 8 : Excitation/Output EquationsRegisters & CountersRegistersShift RegistersSerial In, Serial Out Shift RegisterSerial In, Parallel Out Shift registerParallel In, Serial Out Shift RegisterParallel In, Parallel Out Shift RegisterShift Register Applications Example: 8-Bit Serial AdderCountersSlide 109Ripple Counter ProblemSynchronous CountersSynchronous Serial CounterSynchronous Parallel CounterEECC341 - ShaabanEECC341 - Shaaban#1 Final Review Winter 2001 2-20-2002Final Exam Review•Combinational Logic Building Blocks:–Decoders, Encoders, Multiplexers, Demultiplexers–Implementing functions using decoders, multiplexers.•Combinational Arithmetic Circuits:–Adders, Subtractors, Multipliers, Comparators, shifters.•Sequential Logic Circuits:–Latches, Flip-Flips. •Clocked Synchronous State Machines:–State Machine AnalysisState Machine Analysis–State Machine DesignState Machine Design•Registers & Counters.EECC341 - ShaabanEECC341 - Shaaban#2 Final Review Winter 2001 2-20-2002Binary n-to-2Binary n-to-2nn Decoders Decoders•A binary decoder has n inputs and 2n outputs.•Only the output corresponding to the input value is equal to 1.::ninputsn to 2ndecoder2noutputsEECC341 - ShaabanEECC341 - Shaaban#3 Final Review Winter 2001 2-20-20023-to-8 Binary Decoder3-to-8 Binary Decoderx y z F0F1F2F3F4F5F6F70 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1F1 = x'y'zx zyF0 = x'y'z'F2 = x'yz'F3 = x'yzF5 = xy'zF4 = xy'z'F6 = xyz'F7 = xyzTruth Table: 3-to-8DecoderXYF0F1F2F3F4F5F6F7ZEECC341 - ShaabanEECC341 - Shaaban#4 Final Review Winter 2001 2-20-2002Implementing Functions Using Decoders•Any n-variable logic function, in canonical sum-of-minterms form can be implemented using a single n-to-2n decoder to generate the minterms, and an OR gate to form the sum.–The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate.•Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder with m OR gates.•Suitable when a circuit has many outputs, and each output function is expressed with few minterms.EECC341 - ShaabanEECC341 - Shaaban#5 Final Review Winter 2001 2-20-2002Implementing Functions Using Decoders•Example: Full adderS(x, y, z) =  (1,2,4,7)C(x, y, z) =  (3,5,6,7)3-to-8DecoderS2S1S0xyz01234567SCx y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1EECC341 - ShaabanEECC341 - Shaaban#6 Final Review Winter 2001 2-20-2002Encoders•If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder. e.g. 2n-to-n, priority encoders.•The simplest encoder is a 2n-to-n binary encoder, where it has only one of 2n inputs = 1 and the output is the n-bit