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RIT EECC 341 - Combination Logic Circuit Transient vs Steady state output

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EECC341 - ShaabanEECC341 - Shaaban#1 Lec # 8 Winter 2001 1-9-2002Combinational Logic Circuit Transient Vs. Steady-state Output• Gate propagation delay: The time between an input change and thecorresponding change of the output.• Circuit steady-state output: The output is evaluated when the inputs havebeen stable for a long time relative to the gate delays.• Circuit transient output behavior: The circuit output when one or moreinputs change values.• Example: For an inverter with propagation delay, ∆∆ when input changesfrom 1 to 0:• The circuit analysis done so far ignores propagation delays and considers onlysteady-state output when all propagation delays have completed though all thecircuit gates.XX’1010TimeXX’ ∆∆ ((propagation delay)Steady-state outputTransient output1 → 0 Timing DiagramEECC341 - ShaabanEECC341 - Shaaban#2 Lec # 8 Winter 2001 1-9-2002• Output glitch: A momentary unexpected transient output change (shortpulse) when an input changes and usually caused by gate propagationdelays.• Hazards: A hazard exists in a combinational circuit when it produces anoutput glitch when one or more inputs change.• Types of combinational logic hazards:• Static Hazards:– Static-1 Hazard: The output should be 1 but goes momentary to 0 as a result ofan input change. (possible in AND-OR circuits)– Static-0 Hazard: The output should be 0 but goes momentary to 1 as a result ofan input change. (possible in OR-AND circuits)• Dynamic Hazards: The output changes more than once as a result of asingle input change (impossible in 2-level circuits).• Static hazards can be detected and eliminated for 2-level logic circuitsusing K-maps.Combinational Logic Hazards110100Static-1 HazardStatic-0 Hazard100Dynamic Hazard Example1EECC341 - ShaabanEECC341 - Shaaban#3 Lec # 8 Winter 2001 1-9-2002Example: Circuit with Static-1 Hazard• A static-1 hazard exists in the following AND-OR circuit when X = 1, Y = 1and Z changes from 1 to 0 (assume all gates have propagation delay ∆∆ ):XZYZ’X . Z’Y . ZF1 → 0 110 → 1 1 → 0 Timing Diagram1010TimeZZ’∆∆∆∆Y. Z’1010Y. Z∆∆10FSteady-state outputCircuitK-mapZX0100 01 11 10YZXY012367451 111Y . ZX . Z’1 → 0 → 1EECC341 - ShaabanEECC341 - Shaaban#4 Lec # 8 Winter 2001 1-9-2002Eliminating Static-1 Hazards Using K-maps• A static-1 hazard occurs in AND-OR circuits when an input variableand its complement are connected to two different AND gates.• Static-1 hazards are found using k-maps by finding adjacent 1 cells thatare covered by different product terms.• To eliminate static-1 hazards, additional product terms (primeimplicants) are needed to cover such cells thus covering the transition ofthe variable causing the hazard.• For in the previous example the static-1 hazard is eliminated byincluding the additional product term X . YZX0100 01 11 10YZXY012367451 111X. Y X . Z’Y . ZNew F = X . Z’ + Y . Z + X. Y XZYZ’X . Z’Y . ZFX . YCircuit with static-1 hazard eliminatedEECC341 - ShaabanEECC341 - Shaaban#5 Lec # 8 Winter 2001 1-9-2002Eliminating Static-0 Hazards Using K-maps• A static-0 hazard occurs in OR-AND circuits when an input variableand its complement are connected to two different OR gates.• The procedure to find and eliminate static-0 hazards using K-maps isdone in a dual way to finding static-1 hazards.• Static-0 hazards are found using k-maps by finding adjacent 0 cells thatare covered by different sum terms.• To eliminate static-0 hazards, additional sum terms (prime implicates)are needed to cover such cells thus covering the transition of thevariable causing the


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RIT EECC 341 - Combination Logic Circuit Transient vs Steady state output

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