Programmable Logic Design Techniques II. p. 1Programmable Logic Design Techniques IIAlmost all digital signal processing requires that information be recorded, possiblymanipulated and then stored in some way. Thus it makes sense to design small modulesthat perform basic signal processing operations and then combine them into morecomplex designs when more complex operations are needed. The resulting design ishierarchical with a number layers with increasing complexity. Building a circuit in thismanner is much easier than attempting to cobble together a huge design using only circuitprimitives.In this Lab you will design a module that performs a frequently used operation such as"1-bit" addition. Then you will use it to create a “4-bit” adder. Also, you will use otheralready designed modules to create a relatively complex circuit for recording the numberof events – an "8-bit" up counter. To be successful in this Lab you should review DHp.270-p.284 and the Guides to the Xilinx software and hardware posted on the PHY440WWW site.Problem 1. Create a digital circuit that accepts two "1-bit" binary numbers and outputs a"1-bit sum", i.e. a “1-bit adder”. Simulate the design, download it to the FPGA demoboard and test it.As specified, the circuit has to have at least two inputs (one for each 1-bit number) andone output (for the 1-bit sum). But it is possible that the sum will not fit into1 bit. Forexample, adding two 1-bit numbers like 1 and 1, results in a sum 10(2), which requires 2bits to represent it. For this reason, an extra carry output has to be added to indicate whenthis overflow occurs. And if the adder can have a carry output, then it makes sense that itshould also have a carry input. The truth table for such a “1-bit” adder with carry inputand output is as follows: Input 1 Input 2 Carry Input Sum Output Carry Output 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1Transform the truth table into a gate-level logic design using appropriate gate primitivesfrom the Schematic Library of Xilinx Foundation Series Software.For those of you having difficulties in creating this design on your own, a “hint” is givenbelow:Programmable Logic Design Techniques II. p. 2Suppose you have designed and simulated the “1-bit” adder successfully. Now you haveto assign the three inputs of the circuit to three pins of the XC4003 FPGA which can bedriven by the SW3-1 to SW3-8 switch(es) on the board. Pins # 19, 20, 23, 24, 25, 26, 27and 28are all at your disposal. The outputs may be assigned to any of the pins # 49, 48,47, 46, 45, 50 and 51which drive segments of a single 7-segment LED on the board.Since each LED segment is turned “on” by driving the corresponding pin to logic “0” youmay invert the output signal (as done in the circuit above). Then you will have a LEDsegment “on” when the output of the summer is “1” and not “0”.Now you may wish to create a module that can be saved and used in other designs.First, get rid of the inverters, the input (IBUF) and output buffers (OBUF) and theassociated pins.Input0Input1SumCarry InputCarry OutputProgrammable Logic Design Techniques II. p. 3Next select Hierarchy -> Create Macro Symbol from Current Sheet from the menu.Select a name of your choice for your adder and put in relevant comments. Then save it.It will be appended to the SC library and available for use in future designs.Problem 2. Create a design that accepts two 4-bits numbers (A3....A0 and B3….B0) andoutputs a 4-bit sum (Sum3….Sum0). Make use of your “1-bit” adder module. Simulatethe design, download it to the Xilinx demo board and test it. An example of such a “4-bit” adder is given below. This time you may associate the outputs with pins # 61, 62, 65,66, 57, 58, 59 and 60, which drive 8 LED bars (D9-D16 row) on the Xilinx board.Please, note that the pin ordering is important. Pins # 61 and # 60 should be associatedwith the most and least significant bits of the 8-bit number, respectively. You may invertthe output signal to have the LED segments “on” when the output of the summer is “1”.Also, you may associate pins 19, 20, 23 and 24 with the bits A3.0, and pins 25, 26, 27and 28 with the bits B3.0.A0B0A1B1A2B2A3B3SUM0SUM1SUM2SUM3GNDProgrammable Logic Design Techniques II. p. 4Problem 3. Design an 8-bit counter triggered by an oscillating signal. Use the internal 5-frequency signal generator module, OSC4, to trigger (clock) the counter. Use the 8-bitloadable cascadable bidirectional binary up/down counter with clock enable and clear,CB8LED, to count the events. Direct the output to pins # 61, 62, 65, 66, 57, 58, 59 and60, which drive 8 LED bars (D9-D16 row) on the Xilinx board. Download and test thedesign. Provide external control over the reset/clear, enable/disable and up/down inputsof the counter using switch SW3 (pins # 19, 20, 23, 24, 25, 26, 27 and 28) and theSW5/SPARE push button (associated with pin #18) on the Xilinx demo board.For reference, the CB8CLED module, given below, has the following inputs and outputs:Inputs: UP = “1”/”0” = up/down; D[7:0] – an 8-bit number that can be used to initialize the counter; L = “1”/”0” = enables/disables the usage/download of D[7:0] CE = “1”/”0” = clock enable/disable; C = signal from internal or external clock; CLR = “1” = counter reset (clear);Outputs: TC = “1” indicates that the Terminal (1111 1111 for an up counter) Count has been reached; CEO – to be connected to the CE input of the next counter in a cascade configuration; Q[7:0] – the current number of counts accumulated (an 8-bit number);Programmable Logic Design Techniques II. p. 5 The OSC4 module has four outputs: F8M, F500K, F16K, F490 and F15 providingclock pulses (square-wave signal) with frequency 8 MHz, 500 KHz, 16 KHz, 490 Hz and15 Hz, respectively. A possible design is given below.Please, note that the design relies on the usage of
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