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MSU PHY 440 - qst

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Software ManualsISE Quick Start TutorialAbout This TutorialManual ContentsAdditional ResourcesConventionsTypographicalOnline DocumentTable of ContentsVHDL and Schematic Design FlowTutorial OverviewGetting StartedSoftware RequirementsStarting the ISE SoftwareStopping and Restarting your SessionAccessing HelpDesign Entry (VHDL)Creating a New ProjectModifying Counter Module with Counter TemplateSimulating the Behavioral ModelCreating a Test Bench Waveform SourceInitializing Counter InputsGenerating the Expected Simulation Output ValuesSimulating with ModelSimBehavioral SimulationPost-Place and Route SimulationDesign Entry (Schematic)Creating a Schematic Symbol for the VHDL ModuleCreating a New Top-Level SchematicInstantiating VHDL ModulesWiring the SchematicAdding Net Names to WiresCreating BusesAdding I/O MarkersDesign ImplementationRunning Implement DesignViewing the Design in FloorplannerSimulating the Top-level DesignCreating a Test Bench Waveform SourceInitializing Counter InputsGenerating the Expected ResponsesPost-place and Route SimulationEDIF Design FlowEDIF OverviewDesign EntryCreating a New ProjectDesign ImplementationRunning Implement DesignViewing the Design in FPGA EditorIndexRISE Quick Start TutorialISE Quick Start Tutorial www.xilinx.com 1-800-255-7778www.xilinx.com ISE Quick Start Tutorial1-800-255-7778"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc.ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACT-Floorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company is a service mark of Xilinx, Inc. All other trademarks are the property of their respective owners.Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited.The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2003 Xilinx, Inc. All Rights Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.RISE Quick Start Tutorial www.xilinx.com 1-800-255-7778ISE Quick Start Tutorial www.xilinx.com 5 1-800-255-7778RPrefaceAbout This TutorialThe ISE Quick Start Tutorial is a hands-on learning tool for new users of the ISE software and for users who wish to refresh their knowledge of the software. This tutorial is current for ISE 6.x. The tutorial demonstrates basic set-up and design methods available in the PC version of the ISE software. By the end of the tutorial, you will have a greater understanding of how to implement your own design flow using the ISE software.In the ISE Quick Start Tutorial, you will create a new project called Tutorial, in which you will design a 4-bit counter module, simulate and implement the design, and view the results. Following the ISE Quick Start Tutorial, an appendix, EDIF Design, demonstrates how to implement an existing netlist using the ISE software.Manual ContentsThis manual contains the following chapters:• “VHDL and Schematic Design Flow,” demonstrates how to use the VHDL and schematic design entry tools, how to perform


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MSU PHY 440 - qst

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