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MSU PHY 440 - exp_8_FET_OPAmps_Iv10

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FET, OPAmps I. p. 1 Field Effect Transistors and Op Amps I The Field Effect Transistor This lab begins with some experiments on a junction field effect transistor (JFET), type 2N5458 and then continues with op amps using the TL082/084 dual/quad op amp chips. Details of these devices, including pin-out, can be found on the data sheets in the supplementary reading section on your web page. Items marked with an asterisk (*) should be done before coming to lab. Pinch-off bias Set up the circuit below. Use the LabView program JFET.vi to measure the drain current ID as a fuction of the Gate-Source voltage VGS. Remember that the variable gate voltage is negative and you should keep it in the range 0 to 5V. You should find that the drain current decreases with the gate voltage until a point where it is essentially zero. This is the so-called pinch-off voltage. Compare your answer for the pinch-off voltage with the rather liberal limits given on the data page for “Gate-Source Cutoff Voltage”. Common-source transfer characteristics The program measures the current by measuring the voltage drop across the 1k drain resistor. Make a copy of the computer plot of drain current vs. gate-source voltage and paste it into your notebook. Compare your plot to the one in the data sheet. Are the plots similar? Does your plot have the right curvature? The plot should have the form: IDIDSS1VGSVP2 where ID is the drain current, VGS is the gate-source voltage, and IDSS is the drain current at VGS=0 V. From your plot determine the parameters IDSS and VP. Figure 1: FET Circuit.FET, OPAmps I. p. 2 Common-source JFET amplifier Using the same transistor, build the circuit below with a power supply for VDD and a signal generator for the variable input voltages as shown in Figure 3. For a good operating point, the drain voltage should be between 3 V and 7 V. Measure the quiescent drain voltage for your circuit. (The AC signal on the input is not relevant for this may be disconnected for this part.) The circuit above is an AC amplifier. The output signal at the drain will be larger than the input signal on the gate. Figure 2: Drain Current vs. Gate Source Voltage. Figure 3: FET Amplifier.FET, OPAmps I. p. 3 (a) *Explain why this is an inverting amplifier. (b) The gain of the amplifier depends upon the transconductance gm. From your earlier measurements determine the value of gm =iD/ VGS at your operating point. The units of this parameter are mhos or reciprocal ohms. (c) *The gain is defined as G = Vout/Vin Show that: GgmRD1 gmRS And therefore that you expect a gain of about 2.5 if gm = 1x10-3 mhos, RD=5k and RS=1k. (d) Measure the gain of your amplifier circuit and compare with expectation. Op Amps I Build the circuits below using the TL082 dual or TL084 quad op amp. Remember to connect 15 volt supplies to the chip. Make sure that the indicated grounds include your power supply ground. The voltage follower (a) Use an oscilloscope to compare the input and output. Are they the same? Include a copy of the DPO output showing input and output wave forms. (b) Make the input zero volts by grounding it. Use a DMM to discover whether the output is precisely zero volts. Possible the output will be a few millivolts. That represents offset within the op amp. Figure 4: Voltage Follower.FET, OPAmps I. p. 4 The non-inverting amp (a) *Show mathematically that you expect the gain to be given by 1+ Rf/R1. Measure the gain to verify this using resistor values in the range 3K to 200K. Paste a copy of an example DPO screen in your notebook. The inverting amp (a) *Show mathematically that you expect the gain to be given by –Rf/R1. Measure the gain to verify this using resistor values in the range 3K to 200K. Place a copy of a screen output in your notebook. (b) Replace a fixed resistor by a potentiometer. Can you vary the gain of the amplifier using this control? Figure 5: The non-inverting amp. Figure 6: The inverting


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MSU PHY 440 - exp_8_FET_OPAmps_Iv10

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